| /external/libunwind/src/aarch64/ |
| gen-offsets.c | 9 #define SC(N,X) \
30 SC ("R0", regs[0]);
31 SC ("R1", regs[1]);
32 SC ("R2", regs[2]);
33 SC ("R3", regs[3]);
34 SC ("R4", regs[4]);
35 SC ("R5", regs[5]);
36 SC ("R6", regs[6]);
37 SC ("R7", regs[7]);
38 SC ("R8", regs[8])
[all...] |
| /external/libunwind/src/arm/ |
| gen-offsets.c | 9 #define SC(N,X) \
31 SC ("TRAPNO", trap_no);
32 SC ("ERRORCODE", error_code);
33 SC ("OLDMASK", oldmask);
34 SC ("R0", arm_r0);
35 SC ("R1", arm_r1);
36 SC ("R2", arm_r2);
37 SC ("R3", arm_r3);
38 SC ("R4", arm_r4);
39 SC ("R5", arm_r5)
[all...] |
| /external/libunwind/src/mips/ |
| gen-offsets.c | 8 #define SC(N,X) \
|
| /external/libunwind/src/sh/ |
| gen-offsets.c | 9 #define SC(N,X) \
30 SC ("R0", sc_regs[0]);
31 SC ("R1", sc_regs[1]);
32 SC ("R2", sc_regs[2]);
33 SC ("R3", sc_regs[3]);
34 SC ("R4", sc_regs[4]);
35 SC ("R5", sc_regs[5]);
36 SC ("R6", sc_regs[6]);
37 SC ("R7", sc_regs[7]);
38 SC ("R8", sc_regs[8])
[all...] |
| /prebuilts/go/darwin-x86/src/runtime/internal/atomic/ |
| asm_mips64x.s | 11 #define SC(base, rt) WORD $((070<<26)|((base)<<21)|((rt)<<16))
31 SC(1, 3) // *R1 = R3
110 SC(2, 4) // *R2 = R4
136 SC(2, 3) // *R2 = R3
198 SC(3, 4) // *R3 = R4
228 SC(3, 4) // *R3 = R4
|
| /prebuilts/go/darwin-x86/src/sync/atomic/ |
| asm_mips64x.s | 11 #define SC(base, rt) WORD $((070<<26)|((base)<<21)|((rt)<<16))
24 SC(2, 3) // *R2 = R3
60 SC(1, 3) // *R1 = R3
105 SC(2, 4) // *R2 = R4
|
| /prebuilts/go/linux-x86/src/runtime/internal/atomic/ |
| asm_mips64x.s | 11 #define SC(base, rt) WORD $((070<<26)|((base)<<21)|((rt)<<16))
31 SC(1, 3) // *R1 = R3
110 SC(2, 4) // *R2 = R4
136 SC(2, 3) // *R2 = R3
198 SC(3, 4) // *R3 = R4
228 SC(3, 4) // *R3 = R4
|
| /prebuilts/go/linux-x86/src/sync/atomic/ |
| asm_mips64x.s | 11 #define SC(base, rt) WORD $((070<<26)|((base)<<21)|((rt)<<16))
24 SC(2, 3) // *R2 = R3
60 SC(1, 3) // *R1 = R3
105 SC(2, 4) // *R2 = R4
|
| /external/clang/test/OpenMP/ |
| target_codegen_registration.cpp | 28 // CHECK-DAG: [[SC:%.+]] = type { [16 x i32] }
43 // CHECK-DAG: [[C1:@.+]] = internal global [[SC]]
51 // CHECK-NTARGET-DAG: [[SC:%.+]] = type { [16 x i32] }
209 struct SC {
216 SC() {
222 ~SC() {
382 static SC c1;
|
| target_data_use_device_ptr_ast_print.cpp | 38 struct SC {
50 SC(SB *&_RPtrS) : RPtrS(_RPtrS) {}
|
| target_data_use_device_ptr_messages.cpp | 59 struct SC {
71 SC(SB *&_RPtrS) : RPtrS(_RPtrS) {}
|
| target_is_device_ptr_ast_print.cpp | 83 struct SC {
95 SC(SB *&_RPtrS) : RPtrS(_RPtrS) {}
|
| target_is_device_ptr_messages.cpp | 67 struct SC {
79 SC(SB *&_RPtrS) : RPtrS(_RPtrS) {}
|
| target_map_messages.cpp | 79 struct SC {
91 SC(SB *&_RPtrS) : RPtrS(_RPtrS) {}
113 SC r(p),t(p);
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/Network/IScsiDxe/ |
| Md5.c | 77 #define SC MedStates[(Index2 + 2) & 3]
203 SA += (*Md5_F[Index1]) (SB, SC, SD) + Data[IndexD] + Md5_T[IndexT];
|
| /external/clang/lib/ARCMigrate/ |
| TransProtectedScope.cpp | 42 SwitchCase *SC;
50 CaseInfo() : SC(nullptr), State(St_Unchecked) {}
52 : SC(S), Range(Range), State(St_Unchecked) {}
175 Pass.TA.insertAfterToken(info.SC->getColonLoc(), " {");
|
| /prebuilts/go/darwin-x86/test/ken/ |
| complit.go | 15 type SC struct{ a,b,c []int };
57 test("sc.a[i]", sc.a[i]);
58 test("sc.b[i]", sc.b[i]);
59 test("sc.c[i]", sc.c[i]);
109 var sc = SC{[]int{3201,3202,3203},[]int{3204,3205,3206},[]int{3207,3208,3209}} var
|
| /prebuilts/go/linux-x86/test/ken/ |
| complit.go | 15 type SC struct{ a,b,c []int };
57 test("sc.a[i]", sc.a[i]);
58 test("sc.b[i]", sc.b[i]);
59 test("sc.c[i]", sc.c[i]);
109 var sc = SC{[]int{3201,3202,3203},[]int{3204,3205,3206},[]int{3207,3208,3209}} var
|
| /external/llvm/lib/CodeGen/ |
| MachineTraceMetrics.cpp | 109 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI);
110 if (!SC->isValid())
114 PI = SchedModel.getWriteProcResBegin(SC),
115 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
[all...] |
| /external/llvm/lib/DebugInfo/PDB/Raw/ |
| ModInfo.cpp | 52 SCBytes SC; // First section contribution of this module.
|
| /external/spirv-llvm/lib/SPIRV/libSPIRV/ |
| SPIRVType.cpp | 284 getEncoder(O) << Pointer << SC;
290 Decoder >> PointerId >> SC;
|
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| SetTheory.cpp | 259 const std::vector<Record*> &SC = Set->getSuperClasses();
260 for (unsigned i = 0, e = SC.size(); i != e; ++i)
261 if (Expander *Exp = Expanders.lookup(SC[i]->getName())) {
|
| /external/v8/src/ |
| counters.cc | 106 #define SC(name, caption) \
109 STATS_COUNTER_LIST_1(SC)
110 STATS_COUNTER_LIST_2(SC)
111 #undef SC
113 #define SC(name) \
116 INSTANCE_TYPE_LIST(SC)
117 #undef SC
119 #define SC(name) \
124 CODE_KIND_LIST(SC)
125 #undef SC
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| msp430-decode.c | 86 #define SC(c) OP (1, MSP430_Operand_Immediate, 0, c)
203 SC (0);
222 SC (1);
234 SC (4);
237 SC (2);
253 SC (x);
257 SC (8);
260 SC (-1);
549 ID (MSO_mov); SC ((srcr << 16) + IMMU(2)); DR (dstr);
573 ID (MSO_cmp); SC ((srcr << 16) + IMMU(2)); DR (dstr)
[all...] |
| rl78-decode.c | 119 #define SC(c) OP (1, RL78_Operand_Immediate, 0, c)
257 ID(add); W(); DR(AX); SC(IMMU(2)); Fzac;
319 ID(add); DM(None, SADDR); SC(IMMU(1)); Fzac;
351 ID(add); DR(A); SC(IMMU(1)); Fzac;
411 ID(add); W(); DR(SP); SC(IMMU(1)); Fzac;
503 ID(mov); DM(B, IMMU(2)); SC(IMMU(1));
518 ID(addc); DM(None, SADDR); SC(IMMU(1)); Fzac;
550 ID(addc); DR(A); SC(IMMU(1)); Fzac;
610 ID(sub); W(); DR(SP); SC(IMMU(1)); Fzac;
663 ID(sub); W(); DR(AX); SC(IMMU(2)); Fzac
[all...] |
