| /art/disassembler/ |
| disassembler_x86.h | 25 enum RegFile { GPR, MMX, SSE };
|
| /external/fec/ |
| encode_rs_8.c | 12 static enum {UNKNOWN=0,MMX,SSE,SSE2,ALTIVEC,PORT} cpu_mode;
30 } else if(f & (1<<25)){ /* SSE is present */
31 cpu_mode = SSE;
59 case SSE:
|
| fec.h | 261 extern enum cpu_mode {UNKNOWN=0,PORT,MMX,SSE,SSE2,ALTIVEC} Cpu_mode;
|
| /external/swiftshader/src/Common/ |
| CPUID.cpp | 34 bool CPUID::SSE = detectSSE();
192 return SSE = (registers[3] & 0x02000000) != 0;
|
| CPUID.hpp | 29 static bool supportsMMX2(); // MMX instructions added by SSE: pshufw, pmulhuw, pmovmskb, pavgw/b, pextrw, pinsrw, pmaxsw/ub, etc.
52 static bool SSE;
94 return supportsSSE(); // Coincides with 64-bit integer vector instructions supported by SSE
99 return SSE && enableSSE;
|
| /external/swiftshader/src/OpenGL/libGL/ |
| Display.cpp | 73 int SSE = false;
74 size_t length = sizeof(SSE);
75 sysctlbyname("hw.optional.sse", &SSE, &length, 0, 0);
76 return SSE;
|
| /external/libchrome/base/ |
| cpu.h | 22 SSE,
|
| /device/linaro/bootloader/edk2/Vlv2TbltDevicePkg/Include/Guid/ |
| PlatformCpuInfo.h | 138 UINT8 SSE; // EDX [25]
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/ |
| OhciReg.h | 356 UINT32 SSE:1;
|
| /device/linaro/bootloader/edk2/QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/ |
| OhciReg.h | 356 UINT32 SSE:1;
|
| /external/clang/lib/CodeGen/ |
| TargetInfo.cpp | 840 /// Returns true if this type can be passed in SSE registers with the
856 /// Returns true if this aggregate is small enough to be passed in SSE registers
[all...] |
| CGBuiltin.cpp | [all...] |
| /external/eigen/Eigen/src/Core/util/ |
| Constants.h | 463 SSE = 0x1,
468 Target = SSE
|
| /external/valgrind/VEX/priv/ |
| guest_s390_toIR.c | [all...] |
