| /external/llvm/lib/Target/AArch64/ |
| AArch64ExpandPseudoInsts.cpp | 97 const unsigned ShiftAmt = ToIdx * 16;
100 const uint64_t Chunk = getChunk(Imm, FromIdx) << ShiftAmt;
102 Imm &= ~(0xFFFFLL << ShiftAmt);
114 const unsigned ShiftAmt = ChunkIdx * 16;
134 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
195 unsigned ShiftAmt = 0;
198 for (; ShiftAmt < 64; ShiftAmt += 16) {
199 Imm16 = (UImm >> ShiftAmt) & 0xFFFF;
212 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt));
[all...] |
| AArch64ConditionOptimizer.cpp | 165 unsigned ShiftAmt = AArch64_AM::getShiftValue(I->getOperand(3).getImm());
169 } else if (I->getOperand(2).getImm() << ShiftAmt >= 0xfff) {
|
| AArch64ISelDAGToDAG.cpp | 264 unsigned ShiftAmt;
267 ShiftAmt = 0;
269 ShiftAmt = 12;
274 unsigned ShVal = AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftAmt);
[all...] |
| /external/llvm/lib/Analysis/ |
| DemandedBits.cpp | 147 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1);
148 AB = AOut.lshr(ShiftAmt);
154 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
156 AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
163 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1);
164 AB = AOut.shl(ShiftAmt);
169 AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
176 uint64_t ShiftAmt = CI->getLimitedValue(BitWidth-1);
177 AB = AOut.shl(ShiftAmt);
181 if ((AOut & APInt::getHighBitsSet(BitWidth, ShiftAmt))
[all...] |
| ConstantFolding.cpp | 181 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1);
192 ConstantInt::get(Src->getType(), ShiftAmt));
193 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
213 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1);
218 ConstantInt::get(Src->getType(), ShiftAmt));
219 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
[all...] |
| ValueTracking.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 576 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
577 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
582 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
584 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
590 KnownZero <<= ShiftAmt;
591 KnownOne <<= ShiftAmt;
593 if (ShiftAmt)
594 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
600 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
603 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
[all...] |
| InstCombineCasts.cpp | 565 uint32_t ShiftAmt = KnownZeroMask.logBase2();
567 if (ShiftAmt) {
568 // Perform a logical shr by shiftamt.
570 In = Builder->CreateLShr(In, ConstantInt::get(In->getType(),ShiftAmt),
[all...] |
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineSimplifyDemanded.cpp | 566 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
567 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt));
572 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
574 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
580 KnownZero <<= ShiftAmt;
581 KnownOne <<= ShiftAmt;
583 if (ShiftAmt)
584 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
590 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1);
593 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt));
[all...] |
| InstCombineCasts.cpp | 645 // Perform a logical shr by shiftamt.
784 uint64_t ShiftAmt = Amt->getZExtValue();
785 BitsToClear = ShiftAmt < BitsToClear ? BitsToClear - ShiftAmt : 0;
[all...] |
| InstCombineCalls.cpp | 316 auto ShiftAmt = ConstantInt::get(SVT, Count.zextOrTrunc(BitWidth));
317 auto ShiftVec = Builder.CreateVectorSplat(VWidth, ShiftAmt);
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| ConstantFolding.cpp | 132 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1);
143 ConstantInt::get(Src->getType(), ShiftAmt));
144 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize;
162 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1);
167 ConstantInt::get(Src->getType(), ShiftAmt));
168 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize;
[all...] |
| ValueTracking.cpp | 329 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
330 APInt Mask2(Mask.lshr(ShiftAmt));
334 KnownZero <<= ShiftAmt;
335 KnownOne <<= ShiftAmt;
336 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); // low bits known 0
344 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth);
347 APInt Mask2(Mask.shl(ShiftAmt));
351 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt);
352 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt);
354 KnownZero |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
[all...] |
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| AtomicExpandPass.cpp | 568 Value *ShiftAmt;
582 /// ShiftAmt: Number of bits to right-shift a WordSize value loaded
621 Ret.ShiftAmt = Builder.CreateShl(PtrLSB, 3);
624 Ret.ShiftAmt =
628 Ret.ShiftAmt = Builder.CreateTrunc(Ret.ShiftAmt, Ret.WordType, "ShiftAmt");
630 ConstantInt::get(Ret.WordType, (1 << ValueSize * 8) - 1), Ret.ShiftAmt,
674 Builder.CreateLShr(Loaded, PMV.ShiftAmt), PMV.ValueType);
677 Builder.CreateZExt(NewVal, PMV.WordType), PMV.ShiftAmt);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600ISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsFastISel.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| GVN.cpp | 782 uint64_t ShiftAmt = DL.getTypeStoreSizeInBits(StoredValTy) -
784 StoredVal = IRB.CreateLShr(StoredVal, ShiftAmt, "tmp");
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| GVN.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelDAGToDAG.cpp | [all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
