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  /device/linaro/bootloader/edk2/AppPkg/Applications/Python/Python-2.7.2/Tools/framer/framer/
slots.py 1 """Descriptions of all the slots in Python's type objects."""
10 Slots = (Slot("ob_size"),
58 # give some slots symbolic names
59 TP_NAME = Slots[1]
60 TP_BASICSIZE = Slots[2]
61 TP_DEALLOC = Slots[4]
62 TP_DOC = Slots[20]
63 TP_METHODS = Slots[27]
64 TP_MEMBERS = Slots[28]
  /external/llvm/lib/DebugInfo/CodeView/
TypeTableBuilder.cpp 178 ArrayRef<VFTableSlotKind> Slots = Record.getSlots();
180 Builder.writeUInt16(Slots.size());
181 for (size_t SlotIndex = 0; SlotIndex < Slots.size(); SlotIndex += 2) {
182 uint8_t Byte = static_cast<uint8_t>(Slots[SlotIndex]) << 4;
183 if ((SlotIndex + 1) < Slots.size()) {
184 Byte |= static_cast<uint8_t>(Slots[SlotIndex + 1]);
  /external/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonShuffler.h 30 // Mask of the slots or units that may execute the insn and
32 unsigned Slots, Weight;
38 Slots = s & ~(~0U << HEXAGON_PACKET_SIZE);
42 unsigned getUnits() const { return (Slots); };
62 // Available HVX slots.
73 // Count of adjacent slots that the insn requires to be executed.
122 // Check if the handles are in ascending order by core slots.
126 // Check if the handles are in ascending order by HVX slots.
156 SHUFFLE_ERROR_STORES, ///< No free slots for store insns.
157 SHUFFLE_ERROR_LOADS, ///< No free slots for load insns
    [all...]
  /external/llvm/include/llvm/IR/
Value.h 640 Use *Slots[MaxSlots];
646 Slots[0] = UseList;
659 if (!Slots[I])
664 // Since the uses in Slots[I] originally preceded those in Current, send
665 // Slots[I] in as the left parameter to maintain a stable sort.
666 Current = mergeUseLists(Slots[I], Current, Cmp);
667 Slots[I] = nullptr;
676 Slots[I] = Current;
684 if (Slots[I])
685 // Since the uses in Slots[I] originally preceded those in UseList, sen
    [all...]
  /external/llvm/lib/AsmParser/
LLParser.h 94 SlotMapping *Slots;
144 SlotMapping *Slots = nullptr)
146 Slots(Slots), BlockAddressPFS(nullptr) {}
149 bool parseStandaloneConstantValue(Constant *&C, const SlotMapping *Slots);
152 const SlotMapping *Slots);
167 void restoreParsingState(const SlotMapping *Slots);
  /external/llvm/lib/CodeGen/
LiveIntervalAnalysis.cpp 852 ArrayRef<SlotIndex> Slots;
855 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
858 Slots = getRegMaskSlots();
862 // We are going to enumerate all the register mask slots contained in LI.
865 std::lower_bound(Slots.begin(), Slots.end(), LiveI->start);
866 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
868 // No slots in range, LI begins after the last call.
875 // Loop over all slots overlapping this segment.
885 UsableRegs.clearBitsNotInMask(Bits[SlotI-Slots.begin()])
    [all...]
  /external/llvm/include/llvm/DebugInfo/CodeView/
TypeRecord.h 620 explicit VFTableShapeRecord(ArrayRef<VFTableSlotKind> Slots)
621 : TypeRecord(TypeRecordKind::VFTableShape), SlotsRef(Slots) {}
622 explicit VFTableShapeRecord(std::vector<VFTableSlotKind> Slots)
623 : TypeRecord(TypeRecordKind::VFTableShape), Slots(std::move(Slots)) {}
635 return Slots;
650 std::vector<VFTableSlotKind> Slots;
    [all...]
  /external/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp     [all...]

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