1 /** @file 2 System On Chip Unit (SOCUnit) routines. 3 4 Copyright (c) 2013-2015 Intel Corporation. 5 6 This program and the accompanying materials 7 are licensed and made available under the terms and conditions of the BSD License 8 which accompanies this distribution. The full text of the license may be found at 9 http://opensource.org/licenses/bsd-license.php 10 11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 13 14 **/ 15 16 #include "CommonHeader.h" 17 18 /** Early initialisation of the SOC Unit 19 20 @retval EFI_SUCCESS Operation success. 21 22 **/ 23 EFI_STATUS 24 EFIAPI 25 SocUnitEarlyInitialisation ( 26 VOID 27 ) 28 { 29 UINT32 NewValue; 30 31 // 32 // Set the mixer load resistance 33 // 34 NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0); 35 NewValue &= OCFGPIMIXLOAD_1_0_MASK; 36 QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0, NewValue); 37 38 NewValue = QNCPortIORead (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1); 39 NewValue &= OCFGPIMIXLOAD_1_0_MASK; 40 QNCPortIOWrite (QUARK_SC_PCIE_AFE_SB_PORT_ID, QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1, NewValue); 41 42 return EFI_SUCCESS; 43 } 44 45 /** Tasks to release PCI controller from reset pre wait for PLL Lock. 46 47 @retval EFI_SUCCESS Operation success. 48 49 **/ 50 EFI_STATUS 51 EFIAPI 52 SocUnitReleasePcieControllerPreWaitPllLock ( 53 IN CONST EFI_PLATFORM_TYPE PlatformType 54 ) 55 { 56 UINT32 NewValue; 57 58 // 59 // Assert PERST# and validate time assertion time. 60 // 61 PlatformPERSTAssert (PlatformType); 62 ASSERT (PCIEXP_PERST_MIN_ASSERT_US <= (PCIEXP_DELAY_US_POST_CMNRESET_RESET + PCIEXP_DELAY_US_WAIT_PLL_LOCK + PCIEXP_DELAY_US_POST_SBI_RESET)); 63 64 // 65 // PHY Common lane reset. 66 // 67 NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG); 68 NewValue |= SOCCLKEN_CONFIG_PHY_I_CMNRESET_L; 69 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue); 70 71 // 72 // Wait post common lane reset. 73 // 74 MicroSecondDelay (PCIEXP_DELAY_US_POST_CMNRESET_RESET); 75 76 // 77 // PHY Sideband interface reset. 78 // Controller main reset 79 // 80 NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG); 81 NewValue |= (SOCCLKEN_CONFIG_SBI_RST_100_CORE_B | SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L); 82 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue); 83 84 return EFI_SUCCESS; 85 } 86 87 /** Tasks to release PCI controller from reset after PLL has locked 88 89 @retval EFI_SUCCESS Operation success. 90 91 **/ 92 EFI_STATUS 93 EFIAPI 94 SocUnitReleasePcieControllerPostPllLock ( 95 IN CONST EFI_PLATFORM_TYPE PlatformType 96 ) 97 { 98 UINT32 NewValue; 99 100 // 101 // Controller sideband interface reset. 102 // 103 NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG); 104 NewValue |= SOCCLKEN_CONFIG_SBI_BB_RST_B; 105 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue); 106 107 // 108 // Wait post sideband interface reset. 109 // 110 MicroSecondDelay (PCIEXP_DELAY_US_POST_SBI_RESET); 111 112 // 113 // Deassert PERST#. 114 // 115 PlatformPERSTDeAssert (PlatformType); 116 117 // 118 // Wait post de assert PERST#. 119 // 120 MicroSecondDelay (PCIEXP_DELAY_US_POST_PERST_DEASSERT); 121 122 // 123 // Controller primary interface reset. 124 // 125 NewValue = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG); 126 NewValue |= SOCCLKEN_CONFIG_BB_RST_B; 127 QNCAltPortWrite (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG, NewValue); 128 129 return EFI_SUCCESS; 130 } 131 132
