1 /* 2 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * 7 * Redistributions of source code must retain the above copyright notice, this 8 * list of conditions and the following disclaimer. 9 * 10 * Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * Neither the name of ARM nor the names of its contributors may be used 15 * to endorse or promote products derived from this software without specific 16 * prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 #ifndef __ARCH_H__ 32 #define __ARCH_H__ 33 34 35 /******************************************************************************* 36 * MIDR bit definitions 37 ******************************************************************************/ 38 #define MIDR_IMPL_MASK 0xff 39 #define MIDR_IMPL_SHIFT 0x18 40 #define MIDR_VAR_SHIFT 20 41 #define MIDR_VAR_BITS 4 42 #define MIDR_REV_SHIFT 0 43 #define MIDR_REV_BITS 4 44 #define MIDR_PN_MASK 0xfff 45 #define MIDR_PN_SHIFT 0x4 46 47 /******************************************************************************* 48 * MPIDR macros 49 ******************************************************************************/ 50 #define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK 51 #define MPIDR_CLUSTER_MASK MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS 52 #define MPIDR_AFFINITY_BITS 8 53 #define MPIDR_AFFLVL_MASK 0xff 54 #define MPIDR_AFF0_SHIFT 0 55 #define MPIDR_AFF1_SHIFT 8 56 #define MPIDR_AFF2_SHIFT 16 57 #define MPIDR_AFF3_SHIFT 32 58 #define MPIDR_AFFINITY_MASK 0xff00ffffff 59 #define MPIDR_AFFLVL_SHIFT 3 60 #define MPIDR_AFFLVL0 0 61 #define MPIDR_AFFLVL1 1 62 #define MPIDR_AFFLVL2 2 63 #define MPIDR_AFFLVL3 3 64 /* 65 * The MPIDR_MAX_AFFLVL count starts from 0. Take care to 66 * add one while using this macro to define array sizes. 67 * TODO: Support only the first 3 affinity levels for now. 68 */ 69 #define MPIDR_MAX_AFFLVL 2 70 71 /* Constant to highlight the assumption that MPIDR allocation starts from 0 */ 72 #define FIRST_MPIDR 0 73 74 /******************************************************************************* 75 * Definitions for CPU system register interface to GICv3 76 ******************************************************************************/ 77 #define ICC_SRE_EL1 S3_0_C12_C12_5 78 #define ICC_SRE_EL2 S3_4_C12_C9_5 79 #define ICC_SRE_EL3 S3_6_C12_C12_5 80 #define ICC_CTLR_EL1 S3_0_C12_C12_4 81 #define ICC_CTLR_EL3 S3_6_C12_C12_4 82 #define ICC_PMR_EL1 S3_0_C4_C6_0 83 84 /******************************************************************************* 85 * Generic timer memory mapped registers & offsets 86 ******************************************************************************/ 87 #define CNTCR_OFF 0x000 88 #define CNTFID_OFF 0x020 89 90 #define CNTCR_EN (1 << 0) 91 #define CNTCR_HDBG (1 << 1) 92 #define CNTCR_FCREQ(x) ((x) << 8) 93 94 /******************************************************************************* 95 * System register bit definitions 96 ******************************************************************************/ 97 /* CLIDR definitions */ 98 #define LOUIS_SHIFT 21 99 #define LOC_SHIFT 24 100 #define CLIDR_FIELD_WIDTH 3 101 102 /* CSSELR definitions */ 103 #define LEVEL_SHIFT 1 104 105 /* D$ set/way op type defines */ 106 #define DCISW 0x0 107 #define DCCISW 0x1 108 #define DCCSW 0x2 109 110 /* ID_AA64PFR0_EL1 definitions */ 111 #define ID_AA64PFR0_EL0_SHIFT 0 112 #define ID_AA64PFR0_EL1_SHIFT 4 113 #define ID_AA64PFR0_EL2_SHIFT 8 114 #define ID_AA64PFR0_EL3_SHIFT 12 115 #define ID_AA64PFR0_ELX_MASK 0xf 116 117 /* ID_PFR1_EL1 definitions */ 118 #define ID_PFR1_VIRTEXT_SHIFT 12 119 #define ID_PFR1_VIRTEXT_MASK 0xf 120 #define GET_VIRT_EXT(id) ((id >> ID_PFR1_VIRTEXT_SHIFT) \ 121 & ID_PFR1_VIRTEXT_MASK) 122 123 /* SCTLR definitions */ 124 #define SCTLR_EL2_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ 125 (1 << 18) | (1 << 16) | (1 << 11) | (1 << 5) | \ 126 (1 << 4)) 127 128 #define SCTLR_EL1_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) | \ 129 (1 << 11)) 130 #define SCTLR_AARCH32_EL1_RES1 \ 131 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \ 132 (1 << 3)) 133 134 #define SCTLR_M_BIT (1 << 0) 135 #define SCTLR_A_BIT (1 << 1) 136 #define SCTLR_C_BIT (1 << 2) 137 #define SCTLR_SA_BIT (1 << 3) 138 #define SCTLR_I_BIT (1 << 12) 139 #define SCTLR_WXN_BIT (1 << 19) 140 #define SCTLR_EE_BIT (1 << 25) 141 142 /* CPACR_El1 definitions */ 143 #define CPACR_EL1_FPEN(x) (x << 20) 144 #define CPACR_EL1_FP_TRAP_EL0 0x1 145 #define CPACR_EL1_FP_TRAP_ALL 0x2 146 #define CPACR_EL1_FP_TRAP_NONE 0x3 147 148 /* SCR definitions */ 149 #define SCR_RES1_BITS ((1 << 4) | (1 << 5)) 150 #define SCR_TWE_BIT (1 << 13) 151 #define SCR_TWI_BIT (1 << 12) 152 #define SCR_ST_BIT (1 << 11) 153 #define SCR_RW_BIT (1 << 10) 154 #define SCR_SIF_BIT (1 << 9) 155 #define SCR_HCE_BIT (1 << 8) 156 #define SCR_SMD_BIT (1 << 7) 157 #define SCR_EA_BIT (1 << 3) 158 #define SCR_FIQ_BIT (1 << 2) 159 #define SCR_IRQ_BIT (1 << 1) 160 #define SCR_NS_BIT (1 << 0) 161 #define SCR_VALID_BIT_MASK 0x2f8f 162 163 /* HCR definitions */ 164 #define HCR_RW_BIT (1ull << 31) 165 #define HCR_AMO_BIT (1 << 5) 166 #define HCR_IMO_BIT (1 << 4) 167 #define HCR_FMO_BIT (1 << 3) 168 169 /* CNTHCTL_EL2 definitions */ 170 #define EVNTEN_BIT (1 << 2) 171 #define EL1PCEN_BIT (1 << 1) 172 #define EL1PCTEN_BIT (1 << 0) 173 174 /* CNTKCTL_EL1 definitions */ 175 #define EL0PTEN_BIT (1 << 9) 176 #define EL0VTEN_BIT (1 << 8) 177 #define EL0PCTEN_BIT (1 << 0) 178 #define EL0VCTEN_BIT (1 << 1) 179 #define EVNTEN_BIT (1 << 2) 180 #define EVNTDIR_BIT (1 << 3) 181 #define EVNTI_SHIFT 4 182 #define EVNTI_MASK 0xf 183 184 /* CPTR_EL3 definitions */ 185 #define TCPAC_BIT (1 << 31) 186 #define TTA_BIT (1 << 20) 187 #define TFP_BIT (1 << 10) 188 189 /* CPSR/SPSR definitions */ 190 #define DAIF_FIQ_BIT (1 << 0) 191 #define DAIF_IRQ_BIT (1 << 1) 192 #define DAIF_ABT_BIT (1 << 2) 193 #define DAIF_DBG_BIT (1 << 3) 194 #define SPSR_DAIF_SHIFT 6 195 #define SPSR_DAIF_MASK 0xf 196 197 #define SPSR_AIF_SHIFT 6 198 #define SPSR_AIF_MASK 0x7 199 200 #define SPSR_E_SHIFT 9 201 #define SPSR_E_MASK 0x1 202 #define SPSR_E_LITTLE 0x0 203 #define SPSR_E_BIG 0x1 204 205 #define SPSR_T_SHIFT 5 206 #define SPSR_T_MASK 0x1 207 #define SPSR_T_ARM 0x0 208 #define SPSR_T_THUMB 0x1 209 210 #define DISABLE_ALL_EXCEPTIONS \ 211 (DAIF_FIQ_BIT | DAIF_IRQ_BIT | DAIF_ABT_BIT | DAIF_DBG_BIT) 212 213 214 /* 215 * TCR defintions 216 */ 217 #define TCR_EL3_RES1 ((1UL << 31) | (1UL << 23)) 218 #define TCR_EL1_IPS_SHIFT 32 219 #define TCR_EL3_PS_SHIFT 16 220 221 /* (internal) physical address size bits in EL3/EL1 */ 222 #define TCR_PS_BITS_4GB (0x0) 223 #define TCR_PS_BITS_64GB (0x1) 224 #define TCR_PS_BITS_1TB (0x2) 225 #define TCR_PS_BITS_4TB (0x3) 226 #define TCR_PS_BITS_16TB (0x4) 227 #define TCR_PS_BITS_256TB (0x5) 228 229 #define ADDR_MASK_48_TO_63 0xFFFF000000000000UL 230 #define ADDR_MASK_44_TO_47 0x0000F00000000000UL 231 #define ADDR_MASK_42_TO_43 0x00000C0000000000UL 232 #define ADDR_MASK_40_TO_41 0x0000030000000000UL 233 #define ADDR_MASK_36_TO_39 0x000000F000000000UL 234 #define ADDR_MASK_32_TO_35 0x0000000F00000000UL 235 236 #define TCR_RGN_INNER_NC (0x0 << 8) 237 #define TCR_RGN_INNER_WBA (0x1 << 8) 238 #define TCR_RGN_INNER_WT (0x2 << 8) 239 #define TCR_RGN_INNER_WBNA (0x3 << 8) 240 241 #define TCR_RGN_OUTER_NC (0x0 << 10) 242 #define TCR_RGN_OUTER_WBA (0x1 << 10) 243 #define TCR_RGN_OUTER_WT (0x2 << 10) 244 #define TCR_RGN_OUTER_WBNA (0x3 << 10) 245 246 #define TCR_SH_NON_SHAREABLE (0x0 << 12) 247 #define TCR_SH_OUTER_SHAREABLE (0x2 << 12) 248 #define TCR_SH_INNER_SHAREABLE (0x3 << 12) 249 250 #define MODE_SP_SHIFT 0x0 251 #define MODE_SP_MASK 0x1 252 #define MODE_SP_EL0 0x0 253 #define MODE_SP_ELX 0x1 254 255 #define MODE_RW_SHIFT 0x4 256 #define MODE_RW_MASK 0x1 257 #define MODE_RW_64 0x0 258 #define MODE_RW_32 0x1 259 260 #define MODE_EL_SHIFT 0x2 261 #define MODE_EL_MASK 0x3 262 #define MODE_EL3 0x3 263 #define MODE_EL2 0x2 264 #define MODE_EL1 0x1 265 #define MODE_EL0 0x0 266 267 #define MODE32_SHIFT 0 268 #define MODE32_MASK 0xf 269 #define MODE32_usr 0x0 270 #define MODE32_fiq 0x1 271 #define MODE32_irq 0x2 272 #define MODE32_svc 0x3 273 #define MODE32_mon 0x6 274 #define MODE32_abt 0x7 275 #define MODE32_hyp 0xa 276 #define MODE32_und 0xb 277 #define MODE32_sys 0xf 278 279 #define GET_RW(mode) (((mode) >> MODE_RW_SHIFT) & MODE_RW_MASK) 280 #define GET_EL(mode) (((mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) 281 #define GET_SP(mode) (((mode) >> MODE_SP_SHIFT) & MODE_SP_MASK) 282 #define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK) 283 284 #define SPSR_64(el, sp, daif) \ 285 (MODE_RW_64 << MODE_RW_SHIFT | \ 286 ((el) & MODE_EL_MASK) << MODE_EL_SHIFT | \ 287 ((sp) & MODE_SP_MASK) << MODE_SP_SHIFT | \ 288 ((daif) & SPSR_DAIF_MASK) << SPSR_DAIF_SHIFT) 289 290 #define SPSR_MODE32(mode, isa, endian, aif) \ 291 (MODE_RW_32 << MODE_RW_SHIFT | \ 292 ((mode) & MODE32_MASK) << MODE32_SHIFT | \ 293 ((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \ 294 ((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \ 295 ((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT) 296 297 298 /* Physical timer control register bit fields shifts and masks */ 299 #define CNTP_CTL_ENABLE_SHIFT 0 300 #define CNTP_CTL_IMASK_SHIFT 1 301 #define CNTP_CTL_ISTATUS_SHIFT 2 302 303 #define CNTP_CTL_ENABLE_MASK 1 304 #define CNTP_CTL_IMASK_MASK 1 305 #define CNTP_CTL_ISTATUS_MASK 1 306 307 #define get_cntp_ctl_enable(x) ((x >> CNTP_CTL_ENABLE_SHIFT) & \ 308 CNTP_CTL_ENABLE_MASK) 309 #define get_cntp_ctl_imask(x) ((x >> CNTP_CTL_IMASK_SHIFT) & \ 310 CNTP_CTL_IMASK_MASK) 311 #define get_cntp_ctl_istatus(x) ((x >> CNTP_CTL_ISTATUS_SHIFT) & \ 312 CNTP_CTL_ISTATUS_MASK) 313 314 #define set_cntp_ctl_enable(x) (x |= 1 << CNTP_CTL_ENABLE_SHIFT) 315 #define set_cntp_ctl_imask(x) (x |= 1 << CNTP_CTL_IMASK_SHIFT) 316 317 #define clr_cntp_ctl_enable(x) (x &= ~(1 << CNTP_CTL_ENABLE_SHIFT)) 318 #define clr_cntp_ctl_imask(x) (x &= ~(1 << CNTP_CTL_IMASK_SHIFT)) 319 320 /* Miscellaneous MMU related constants */ 321 #define NUM_2MB_IN_GB (1 << 9) 322 #define NUM_4K_IN_2MB (1 << 9) 323 #define NUM_GB_IN_4GB (1 << 2) 324 325 #define TWO_MB_SHIFT 21 326 #define ONE_GB_SHIFT 30 327 #define FOUR_KB_SHIFT 12 328 329 #define ONE_GB_INDEX(x) ((x) >> ONE_GB_SHIFT) 330 #define TWO_MB_INDEX(x) ((x) >> TWO_MB_SHIFT) 331 #define FOUR_KB_INDEX(x) ((x) >> FOUR_KB_SHIFT) 332 333 #define INVALID_DESC 0x0 334 #define BLOCK_DESC 0x1 335 #define TABLE_DESC 0x3 336 337 #define FIRST_LEVEL_DESC_N ONE_GB_SHIFT 338 #define SECOND_LEVEL_DESC_N TWO_MB_SHIFT 339 #define THIRD_LEVEL_DESC_N FOUR_KB_SHIFT 340 341 #define LEVEL1 1 342 #define LEVEL2 2 343 #define LEVEL3 3 344 345 #define XN (1ull << 2) 346 #define PXN (1ull << 1) 347 #define CONT_HINT (1ull << 0) 348 349 #define UPPER_ATTRS(x) (x & 0x7) << 52 350 #define NON_GLOBAL (1 << 9) 351 #define ACCESS_FLAG (1 << 8) 352 #define NSH (0x0 << 6) 353 #define OSH (0x2 << 6) 354 #define ISH (0x3 << 6) 355 356 #define PAGE_SIZE_SHIFT FOUR_KB_SHIFT 357 #define PAGE_SIZE (1 << PAGE_SIZE_SHIFT) 358 #define PAGE_SIZE_MASK (PAGE_SIZE - 1) 359 #define IS_PAGE_ALIGNED(addr) (((addr) & PAGE_SIZE_MASK) == 0) 360 361 #define XLAT_ENTRY_SIZE_SHIFT 3 /* Each MMU table entry is 8 bytes (1 << 3) */ 362 #define XLAT_ENTRY_SIZE (1 << XLAT_ENTRY_SIZE_SHIFT) 363 364 #define XLAT_TABLE_SIZE_SHIFT PAGE_SIZE_SHIFT 365 #define XLAT_TABLE_SIZE (1 << XLAT_TABLE_SIZE_SHIFT) 366 367 /* Values for number of entries in each MMU translation table */ 368 #define XLAT_TABLE_ENTRIES_SHIFT (XLAT_TABLE_SIZE_SHIFT - XLAT_ENTRY_SIZE_SHIFT) 369 #define XLAT_TABLE_ENTRIES (1 << XLAT_TABLE_ENTRIES_SHIFT) 370 #define XLAT_TABLE_ENTRIES_MASK (XLAT_TABLE_ENTRIES - 1) 371 372 /* Values to convert a memory address to an index into a translation table */ 373 #define L3_XLAT_ADDRESS_SHIFT PAGE_SIZE_SHIFT 374 #define L2_XLAT_ADDRESS_SHIFT (L3_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 375 #define L1_XLAT_ADDRESS_SHIFT (L2_XLAT_ADDRESS_SHIFT + XLAT_TABLE_ENTRIES_SHIFT) 376 377 /* 378 * AP[1] bit is ignored by hardware and is 379 * treated as if it is One in EL2/EL3 380 */ 381 #define AP_RO (0x1 << 5) 382 #define AP_RW (0x0 << 5) 383 384 #define NS (0x1 << 3) 385 #define ATTR_SO_INDEX 0x2 386 #define ATTR_DEVICE_INDEX 0x1 387 #define ATTR_IWBWA_OWBWA_NTR_INDEX 0x0 388 #define LOWER_ATTRS(x) (((x) & 0xfff) << 2) 389 #define ATTR_SO (0x0) 390 #define ATTR_DEVICE (0x4) 391 #define ATTR_IWBWA_OWBWA_NTR (0xff) 392 #define MAIR_ATTR_SET(attr, index) (attr << (index << 3)) 393 394 /* Exception Syndrome register bits and bobs */ 395 #define ESR_EC_SHIFT 26 396 #define ESR_EC_MASK 0x3f 397 #define ESR_EC_LENGTH 6 398 #define EC_UNKNOWN 0x0 399 #define EC_WFE_WFI 0x1 400 #define EC_AARCH32_CP15_MRC_MCR 0x3 401 #define EC_AARCH32_CP15_MRRC_MCRR 0x4 402 #define EC_AARCH32_CP14_MRC_MCR 0x5 403 #define EC_AARCH32_CP14_LDC_STC 0x6 404 #define EC_FP_SIMD 0x7 405 #define EC_AARCH32_CP10_MRC 0x8 406 #define EC_AARCH32_CP14_MRRC_MCRR 0xc 407 #define EC_ILLEGAL 0xe 408 #define EC_AARCH32_SVC 0x11 409 #define EC_AARCH32_HVC 0x12 410 #define EC_AARCH32_SMC 0x13 411 #define EC_AARCH64_SVC 0x15 412 #define EC_AARCH64_HVC 0x16 413 #define EC_AARCH64_SMC 0x17 414 #define EC_AARCH64_SYS 0x18 415 #define EC_IABORT_LOWER_EL 0x20 416 #define EC_IABORT_CUR_EL 0x21 417 #define EC_PC_ALIGN 0x22 418 #define EC_DABORT_LOWER_EL 0x24 419 #define EC_DABORT_CUR_EL 0x25 420 #define EC_SP_ALIGN 0x26 421 #define EC_AARCH32_FP 0x28 422 #define EC_AARCH64_FP 0x2c 423 #define EC_SERROR 0x2f 424 425 #define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK 426 427 /******************************************************************************* 428 * Definitions of register offsets and fields in the CNTCTLBase Frame of the 429 * system level implementation of the Generic Timer. 430 ******************************************************************************/ 431 #define CNTNSAR 0x4 432 #define CNTNSAR_NS_SHIFT(x) x 433 434 #define CNTACR_BASE(x) (0x40 + (x << 2)) 435 #define CNTACR_RPCT_SHIFT 0x0 436 #define CNTACR_RVCT_SHIFT 0x1 437 #define CNTACR_RFRQ_SHIFT 0x2 438 #define CNTACR_RVOFF_SHIFT 0x3 439 #define CNTACR_RWVT_SHIFT 0x4 440 #define CNTACR_RWPT_SHIFT 0x5 441 442 #endif /* __ARCH_H__ */ 443
