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      1 //===-- X86ISelLowering.h - X86 DAG Lowering Interface ----------*- C++ -*-===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file defines the interfaces that X86 uses to lower LLVM code into a
     11 // selection DAG.
     12 //
     13 //===----------------------------------------------------------------------===//
     14 
     15 #ifndef X86ISELLOWERING_H
     16 #define X86ISELLOWERING_H
     17 
     18 #include "X86Subtarget.h"
     19 #include "X86RegisterInfo.h"
     20 #include "X86MachineFunctionInfo.h"
     21 #include "llvm/Target/TargetLowering.h"
     22 #include "llvm/Target/TargetOptions.h"
     23 #include "llvm/CodeGen/FastISel.h"
     24 #include "llvm/CodeGen/SelectionDAG.h"
     25 #include "llvm/CodeGen/CallingConvLower.h"
     26 
     27 namespace llvm {
     28   namespace X86ISD {
     29     // X86 Specific DAG Nodes
     30     enum NodeType {
     31       // Start the numbering where the builtin ops leave off.
     32       FIRST_NUMBER = ISD::BUILTIN_OP_END,
     33 
     34       /// BSF - Bit scan forward.
     35       /// BSR - Bit scan reverse.
     36       BSF,
     37       BSR,
     38 
     39       /// SHLD, SHRD - Double shift instructions. These correspond to
     40       /// X86::SHLDxx and X86::SHRDxx instructions.
     41       SHLD,
     42       SHRD,
     43 
     44       /// FAND - Bitwise logical AND of floating point values. This corresponds
     45       /// to X86::ANDPS or X86::ANDPD.
     46       FAND,
     47 
     48       /// FOR - Bitwise logical OR of floating point values. This corresponds
     49       /// to X86::ORPS or X86::ORPD.
     50       FOR,
     51 
     52       /// FXOR - Bitwise logical XOR of floating point values. This corresponds
     53       /// to X86::XORPS or X86::XORPD.
     54       FXOR,
     55 
     56       /// FSRL - Bitwise logical right shift of floating point values. These
     57       /// corresponds to X86::PSRLDQ.
     58       FSRL,
     59 
     60       /// CALL - These operations represent an abstract X86 call
     61       /// instruction, which includes a bunch of information.  In particular the
     62       /// operands of these node are:
     63       ///
     64       ///     #0 - The incoming token chain
     65       ///     #1 - The callee
     66       ///     #2 - The number of arg bytes the caller pushes on the stack.
     67       ///     #3 - The number of arg bytes the callee pops off the stack.
     68       ///     #4 - The value to pass in AL/AX/EAX (optional)
     69       ///     #5 - The value to pass in DL/DX/EDX (optional)
     70       ///
     71       /// The result values of these nodes are:
     72       ///
     73       ///     #0 - The outgoing token chain
     74       ///     #1 - The first register result value (optional)
     75       ///     #2 - The second register result value (optional)
     76       ///
     77       CALL,
     78 
     79       /// RDTSC_DAG - This operation implements the lowering for
     80       /// readcyclecounter
     81       RDTSC_DAG,
     82 
     83       /// X86 compare and logical compare instructions.
     84       CMP, COMI, UCOMI,
     85 
     86       /// X86 bit-test instructions.
     87       BT,
     88 
     89       /// X86 SetCC. Operand 0 is condition code, and operand 1 is the EFLAGS
     90       /// operand, usually produced by a CMP instruction.
     91       SETCC,
     92 
     93       // Same as SETCC except it's materialized with a sbb and the value is all
     94       // one's or all zero's.
     95       SETCC_CARRY,  // R = carry_bit ? ~0 : 0
     96 
     97       /// X86 FP SETCC, implemented with CMP{cc}SS/CMP{cc}SD.
     98       /// Operands are two FP values to compare; result is a mask of
     99       /// 0s or 1s.  Generally DTRT for C/C++ with NaNs.
    100       FSETCCss, FSETCCsd,
    101 
    102       /// X86 MOVMSK{pd|ps}, extracts sign bits of two or four FP values,
    103       /// result in an integer GPR.  Needs masking for scalar result.
    104       FGETSIGNx86,
    105 
    106       /// X86 conditional moves. Operand 0 and operand 1 are the two values
    107       /// to select from. Operand 2 is the condition code, and operand 3 is the
    108       /// flag operand produced by a CMP or TEST instruction. It also writes a
    109       /// flag result.
    110       CMOV,
    111 
    112       /// X86 conditional branches. Operand 0 is the chain operand, operand 1
    113       /// is the block to branch if condition is true, operand 2 is the
    114       /// condition code, and operand 3 is the flag operand produced by a CMP
    115       /// or TEST instruction.
    116       BRCOND,
    117 
    118       /// Return with a flag operand. Operand 0 is the chain operand, operand
    119       /// 1 is the number of bytes of stack to pop.
    120       RET_FLAG,
    121 
    122       /// REP_STOS - Repeat fill, corresponds to X86::REP_STOSx.
    123       REP_STOS,
    124 
    125       /// REP_MOVS - Repeat move, corresponds to X86::REP_MOVSx.
    126       REP_MOVS,
    127 
    128       /// GlobalBaseReg - On Darwin, this node represents the result of the popl
    129       /// at function entry, used for PIC code.
    130       GlobalBaseReg,
    131 
    132       /// Wrapper - A wrapper node for TargetConstantPool,
    133       /// TargetExternalSymbol, and TargetGlobalAddress.
    134       Wrapper,
    135 
    136       /// WrapperRIP - Special wrapper used under X86-64 PIC mode for RIP
    137       /// relative displacements.
    138       WrapperRIP,
    139 
    140       /// MOVQ2DQ - Copies a 64-bit value from an MMX vector to the low word
    141       /// of an XMM vector, with the high word zero filled.
    142       MOVQ2DQ,
    143 
    144       /// MOVDQ2Q - Copies a 64-bit value from the low word of an XMM vector
    145       /// to an MMX vector.  If you think this is too close to the previous
    146       /// mnemonic, so do I; blame Intel.
    147       MOVDQ2Q,
    148 
    149       /// vector to a GPR.
    150       MMX_MOVD2W,
    151 
    152       /// MMX_MOVW2D - Copies a GPR into the low 32-bit word of a MMX vector
    153       /// and zero out the high word.
    154       MMX_MOVW2D,
    155 
    156       /// PEXTRB - Extract an 8-bit value from a vector and zero extend it to
    157       /// i32, corresponds to X86::PEXTRB.
    158       PEXTRB,
    159 
    160       /// PEXTRW - Extract a 16-bit value from a vector and zero extend it to
    161       /// i32, corresponds to X86::PEXTRW.
    162       PEXTRW,
    163 
    164       /// INSERTPS - Insert any element of a 4 x float vector into any element
    165       /// of a destination 4 x floatvector.
    166       INSERTPS,
    167 
    168       /// PINSRB - Insert the lower 8-bits of a 32-bit value to a vector,
    169       /// corresponds to X86::PINSRB.
    170       PINSRB,
    171 
    172       /// PINSRW - Insert the lower 16-bits of a 32-bit value to a vector,
    173       /// corresponds to X86::PINSRW.
    174       PINSRW, MMX_PINSRW,
    175 
    176       /// PSHUFB - Shuffle 16 8-bit values within a vector.
    177       PSHUFB,
    178 
    179       /// ANDNP - Bitwise Logical AND NOT of Packed FP values.
    180       ANDNP,
    181 
    182       /// PSIGNB/W/D - Copy integer sign.
    183       PSIGNB, PSIGNW, PSIGND,
    184 
    185       /// BLEND family of opcodes
    186       BLENDV,
    187 
    188       /// FHADD - Floating point horizontal add.
    189       FHADD,
    190 
    191       /// FHSUB - Floating point horizontal sub.
    192       FHSUB,
    193 
    194       /// FMAX, FMIN - Floating point max and min.
    195       ///
    196       FMAX, FMIN,
    197 
    198       /// FRSQRT, FRCP - Floating point reciprocal-sqrt and reciprocal
    199       /// approximation.  Note that these typically require refinement
    200       /// in order to obtain suitable precision.
    201       FRSQRT, FRCP,
    202 
    203       // TLSADDR - Thread Local Storage.
    204       TLSADDR,
    205 
    206       // TLSCALL - Thread Local Storage.  When calling to an OS provided
    207       // thunk at the address from an earlier relocation.
    208       TLSCALL,
    209 
    210       // EH_RETURN - Exception Handling helpers.
    211       EH_RETURN,
    212 
    213       /// TC_RETURN - Tail call return.
    214       ///   operand #0 chain
    215       ///   operand #1 callee (register or absolute)
    216       ///   operand #2 stack adjustment
    217       ///   operand #3 optional in flag
    218       TC_RETURN,
    219 
    220       // VZEXT_MOVL - Vector move low and zero extend.
    221       VZEXT_MOVL,
    222 
    223       // VSHL, VSRL - Vector logical left / right shift.
    224       VSHL, VSRL,
    225 
    226       // CMPPD, CMPPS - Vector double/float comparison.
    227       // CMPPD, CMPPS - Vector double/float comparison.
    228       CMPPD, CMPPS,
    229 
    230       // PCMP* - Vector integer comparisons.
    231       PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ,
    232       PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ,
    233 
    234       // ADD, SUB, SMUL, etc. - Arithmetic operations with FLAGS results.
    235       ADD, SUB, ADC, SBB, SMUL,
    236       INC, DEC, OR, XOR, AND,
    237 
    238       ANDN, // ANDN - Bitwise AND NOT with FLAGS results.
    239 
    240       UMUL, // LOW, HI, FLAGS = umul LHS, RHS
    241 
    242       // MUL_IMM - X86 specific multiply by immediate.
    243       MUL_IMM,
    244 
    245       // PTEST - Vector bitwise comparisons
    246       PTEST,
    247 
    248       // TESTP - Vector packed fp sign bitwise comparisons
    249       TESTP,
    250 
    251       // Several flavors of instructions with vector shuffle behaviors.
    252       PALIGN,
    253       PSHUFD,
    254       PSHUFHW,
    255       PSHUFLW,
    256       PSHUFHW_LD,
    257       PSHUFLW_LD,
    258       SHUFPD,
    259       SHUFPS,
    260       MOVDDUP,
    261       MOVSHDUP,
    262       MOVSLDUP,
    263       MOVSHDUP_LD,
    264       MOVSLDUP_LD,
    265       MOVLHPS,
    266       MOVLHPD,
    267       MOVHLPS,
    268       MOVHLPD,
    269       MOVLPS,
    270       MOVLPD,
    271       MOVSD,
    272       MOVSS,
    273       UNPCKLPS,
    274       UNPCKLPD,
    275       VUNPCKLPSY,
    276       VUNPCKLPDY,
    277       UNPCKHPS,
    278       UNPCKHPD,
    279       VUNPCKHPSY,
    280       VUNPCKHPDY,
    281       PUNPCKLBW,
    282       PUNPCKLWD,
    283       PUNPCKLDQ,
    284       PUNPCKLQDQ,
    285       PUNPCKHBW,
    286       PUNPCKHWD,
    287       PUNPCKHDQ,
    288       PUNPCKHQDQ,
    289       VPERMILPS,
    290       VPERMILPSY,
    291       VPERMILPD,
    292       VPERMILPDY,
    293       VPERM2F128,
    294       VBROADCAST,
    295 
    296       // VASTART_SAVE_XMM_REGS - Save xmm argument registers to the stack,
    297       // according to %al. An operator is needed so that this can be expanded
    298       // with control flow.
    299       VASTART_SAVE_XMM_REGS,
    300 
    301       // WIN_ALLOCA - Windows's _chkstk call to do stack probing.
    302       WIN_ALLOCA,
    303 
    304       // SEG_ALLOCA - For allocating variable amounts of stack space when using
    305       // segmented stacks. Check if the current stacklet has enough space, and
    306       // falls back to heap allocation if not.
    307       SEG_ALLOCA,
    308 
    309       // Memory barrier
    310       MEMBARRIER,
    311       MFENCE,
    312       SFENCE,
    313       LFENCE,
    314 
    315       // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
    316       // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
    317       // Atomic 64-bit binary operations.
    318       ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE,
    319       ATOMSUB64_DAG,
    320       ATOMOR64_DAG,
    321       ATOMXOR64_DAG,
    322       ATOMAND64_DAG,
    323       ATOMNAND64_DAG,
    324       ATOMSWAP64_DAG,
    325 
    326       // LCMPXCHG_DAG, LCMPXCHG8_DAG, LCMPXCHG16_DAG - Compare and swap.
    327       LCMPXCHG_DAG,
    328       LCMPXCHG8_DAG,
    329       LCMPXCHG16_DAG,
    330 
    331       // VZEXT_LOAD - Load, scalar_to_vector, and zero extend.
    332       VZEXT_LOAD,
    333 
    334       // FNSTCW16m - Store FP control world into i16 memory.
    335       FNSTCW16m,
    336 
    337       /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the
    338       /// integer destination in memory and a FP reg source.  This corresponds
    339       /// to the X86::FIST*m instructions and the rounding mode change stuff. It
    340       /// has two inputs (token chain and address) and two outputs (int value
    341       /// and token chain).
    342       FP_TO_INT16_IN_MEM,
    343       FP_TO_INT32_IN_MEM,
    344       FP_TO_INT64_IN_MEM,
    345 
    346       /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the
    347       /// integer source in memory and FP reg result.  This corresponds to the
    348       /// X86::FILD*m instructions. It has three inputs (token chain, address,
    349       /// and source type) and two outputs (FP value and token chain). FILD_FLAG
    350       /// also produces a flag).
    351       FILD,
    352       FILD_FLAG,
    353 
    354       /// FLD - This instruction implements an extending load to FP stack slots.
    355       /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain
    356       /// operand, ptr to load from, and a ValueType node indicating the type
    357       /// to load to.
    358       FLD,
    359 
    360       /// FST - This instruction implements a truncating store to FP stack
    361       /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a
    362       /// chain operand, value to store, address, and a ValueType to store it
    363       /// as.
    364       FST,
    365 
    366       /// VAARG_64 - This instruction grabs the address of the next argument
    367       /// from a va_list. (reads and modifies the va_list in memory)
    368       VAARG_64
    369 
    370       // WARNING: Do not add anything in the end unless you want the node to
    371       // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be
    372       // thought as target memory ops!
    373     };
    374   }
    375 
    376   /// Define some predicates that are used for node matching.
    377   namespace X86 {
    378     /// isPSHUFDMask - Return true if the specified VECTOR_SHUFFLE operand
    379     /// specifies a shuffle of elements that is suitable for input to PSHUFD.
    380     bool isPSHUFDMask(ShuffleVectorSDNode *N);
    381 
    382     /// isPSHUFHWMask - Return true if the specified VECTOR_SHUFFLE operand
    383     /// specifies a shuffle of elements that is suitable for input to PSHUFD.
    384     bool isPSHUFHWMask(ShuffleVectorSDNode *N);
    385 
    386     /// isPSHUFLWMask - Return true if the specified VECTOR_SHUFFLE operand
    387     /// specifies a shuffle of elements that is suitable for input to PSHUFD.
    388     bool isPSHUFLWMask(ShuffleVectorSDNode *N);
    389 
    390     /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand
    391     /// specifies a shuffle of elements that is suitable for input to SHUFP*.
    392     bool isSHUFPMask(ShuffleVectorSDNode *N);
    393 
    394     /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand
    395     /// specifies a shuffle of elements that is suitable for input to MOVHLPS.
    396     bool isMOVHLPSMask(ShuffleVectorSDNode *N);
    397 
    398     /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form
    399     /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef,
    400     /// <2, 3, 2, 3>
    401     bool isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N);
    402 
    403     /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand
    404     /// specifies a shuffle of elements that is suitable for MOVLP{S|D}.
    405     bool isMOVLPMask(ShuffleVectorSDNode *N);
    406 
    407     /// isMOVHPMask - Return true if the specified VECTOR_SHUFFLE operand
    408     /// specifies a shuffle of elements that is suitable for MOVHP{S|D}.
    409     /// as well as MOVLHPS.
    410     bool isMOVLHPSMask(ShuffleVectorSDNode *N);
    411 
    412     /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand
    413     /// specifies a shuffle of elements that is suitable for input to UNPCKL.
    414     bool isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
    415 
    416     /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand
    417     /// specifies a shuffle of elements that is suitable for input to UNPCKH.
    418     bool isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat = false);
    419 
    420     /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form
    421     /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef,
    422     /// <0, 0, 1, 1>
    423     bool isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N);
    424 
    425     /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form
    426     /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef,
    427     /// <2, 2, 3, 3>
    428     bool isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N);
    429 
    430     /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand
    431     /// specifies a shuffle of elements that is suitable for input to MOVSS,
    432     /// MOVSD, and MOVD, i.e. setting the lowest element.
    433     bool isMOVLMask(ShuffleVectorSDNode *N);
    434 
    435     /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand
    436     /// specifies a shuffle of elements that is suitable for input to MOVSHDUP.
    437     bool isMOVSHDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget);
    438 
    439     /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand
    440     /// specifies a shuffle of elements that is suitable for input to MOVSLDUP.
    441     bool isMOVSLDUPMask(ShuffleVectorSDNode *N, const X86Subtarget *Subtarget);
    442 
    443     /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand
    444     /// specifies a shuffle of elements that is suitable for input to MOVDDUP.
    445     bool isMOVDDUPMask(ShuffleVectorSDNode *N);
    446 
    447     /// isVEXTRACTF128Index - Return true if the specified
    448     /// EXTRACT_SUBVECTOR operand specifies a vector extract that is
    449     /// suitable for input to VEXTRACTF128.
    450     bool isVEXTRACTF128Index(SDNode *N);
    451 
    452     /// isVINSERTF128Index - Return true if the specified
    453     /// INSERT_SUBVECTOR operand specifies a subvector insert that is
    454     /// suitable for input to VINSERTF128.
    455     bool isVINSERTF128Index(SDNode *N);
    456 
    457     /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle
    458     /// the specified isShuffleMask VECTOR_SHUFFLE mask with PSHUF* and SHUFP*
    459     /// instructions.
    460     unsigned getShuffleSHUFImmediate(SDNode *N);
    461 
    462     /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle
    463     /// the specified VECTOR_SHUFFLE mask with PSHUFHW instruction.
    464     unsigned getShufflePSHUFHWImmediate(SDNode *N);
    465 
    466     /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle
    467     /// the specified VECTOR_SHUFFLE mask with PSHUFLW instruction.
    468     unsigned getShufflePSHUFLWImmediate(SDNode *N);
    469 
    470     /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle
    471     /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction.
    472     unsigned getShufflePALIGNRImmediate(SDNode *N);
    473 
    474     /// getExtractVEXTRACTF128Immediate - Return the appropriate
    475     /// immediate to extract the specified EXTRACT_SUBVECTOR index
    476     /// with VEXTRACTF128 instructions.
    477     unsigned getExtractVEXTRACTF128Immediate(SDNode *N);
    478 
    479     /// getInsertVINSERTF128Immediate - Return the appropriate
    480     /// immediate to insert at the specified INSERT_SUBVECTOR index
    481     /// with VINSERTF128 instructions.
    482     unsigned getInsertVINSERTF128Immediate(SDNode *N);
    483 
    484     /// isZeroNode - Returns true if Elt is a constant zero or a floating point
    485     /// constant +0.0.
    486     bool isZeroNode(SDValue Elt);
    487 
    488     /// isOffsetSuitableForCodeModel - Returns true of the given offset can be
    489     /// fit into displacement field of the instruction.
    490     bool isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M,
    491                                       bool hasSymbolicDisplacement = true);
    492 
    493 
    494     /// isCalleePop - Determines whether the callee is required to pop its
    495     /// own arguments. Callee pop is necessary to support tail calls.
    496     bool isCalleePop(CallingConv::ID CallingConv,
    497                      bool is64Bit, bool IsVarArg, bool TailCallOpt);
    498   }
    499 
    500   //===--------------------------------------------------------------------===//
    501   //  X86TargetLowering - X86 Implementation of the TargetLowering interface
    502   class X86TargetLowering : public TargetLowering {
    503   public:
    504     explicit X86TargetLowering(X86TargetMachine &TM);
    505 
    506     virtual unsigned getJumpTableEncoding() const;
    507 
    508     virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
    509 
    510     virtual const MCExpr *
    511     LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
    512                               const MachineBasicBlock *MBB, unsigned uid,
    513                               MCContext &Ctx) const;
    514 
    515     /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
    516     /// jumptable.
    517     virtual SDValue getPICJumpTableRelocBase(SDValue Table,
    518                                              SelectionDAG &DAG) const;
    519     virtual const MCExpr *
    520     getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
    521                                  unsigned JTI, MCContext &Ctx) const;
    522 
    523     /// getStackPtrReg - Return the stack pointer register we are using: either
    524     /// ESP or RSP.
    525     unsigned getStackPtrReg() const { return X86StackPtr; }
    526 
    527     /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
    528     /// function arguments in the caller parameter area. For X86, aggregates
    529     /// that contains are placed at 16-byte boundaries while the rest are at
    530     /// 4-byte boundaries.
    531     virtual unsigned getByValTypeAlignment(Type *Ty) const;
    532 
    533     /// getOptimalMemOpType - Returns the target specific optimal type for load
    534     /// and store operations as a result of memset, memcpy, and memmove
    535     /// lowering. If DstAlign is zero that means it's safe to destination
    536     /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
    537     /// means there isn't a need to check it against alignment requirement,
    538     /// probably because the source does not need to be loaded. If
    539     /// 'NonScalarIntSafe' is true, that means it's safe to return a
    540     /// non-scalar-integer type, e.g. empty string source, constant, or loaded
    541     /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
    542     /// constant so it does not need to be loaded.
    543     /// It returns EVT::Other if the type should be determined using generic
    544     /// target-independent logic.
    545     virtual EVT
    546     getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
    547                         bool NonScalarIntSafe, bool MemcpyStrSrc,
    548                         MachineFunction &MF) const;
    549 
    550     /// allowsUnalignedMemoryAccesses - Returns true if the target allows
    551     /// unaligned memory accesses. of the specified type.
    552     virtual bool allowsUnalignedMemoryAccesses(EVT VT) const {
    553       return true;
    554     }
    555 
    556     /// LowerOperation - Provide custom lowering hooks for some operations.
    557     ///
    558     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
    559 
    560     /// ReplaceNodeResults - Replace the results of node with an illegal result
    561     /// type with new values built out of custom code.
    562     ///
    563     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
    564                                     SelectionDAG &DAG) const;
    565 
    566 
    567     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
    568 
    569     /// isTypeDesirableForOp - Return true if the target has native support for
    570     /// the specified value type and it is 'desirable' to use the type for the
    571     /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
    572     /// instruction encodings are longer and some i16 instructions are slow.
    573     virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
    574 
    575     /// isTypeDesirable - Return true if the target has native support for the
    576     /// specified value type and it is 'desirable' to use the type. e.g. On x86
    577     /// i16 is legal, but undesirable since i16 instruction encodings are longer
    578     /// and some i16 instructions are slow.
    579     virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
    580 
    581     virtual MachineBasicBlock *
    582       EmitInstrWithCustomInserter(MachineInstr *MI,
    583                                   MachineBasicBlock *MBB) const;
    584 
    585 
    586     /// getTargetNodeName - This method returns the name of a target specific
    587     /// DAG node.
    588     virtual const char *getTargetNodeName(unsigned Opcode) const;
    589 
    590     /// getSetCCResultType - Return the value type to use for ISD::SETCC.
    591     virtual EVT getSetCCResultType(EVT VT) const;
    592 
    593     /// computeMaskedBitsForTargetNode - Determine which of the bits specified
    594     /// in Mask are known to be either zero or one and return them in the
    595     /// KnownZero/KnownOne bitsets.
    596     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
    597                                                 const APInt &Mask,
    598                                                 APInt &KnownZero,
    599                                                 APInt &KnownOne,
    600                                                 const SelectionDAG &DAG,
    601                                                 unsigned Depth = 0) const;
    602 
    603     // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
    604     // operation that are sign bits.
    605     virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
    606                                                      unsigned Depth) const;
    607 
    608     virtual bool
    609     isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
    610 
    611     SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
    612 
    613     virtual bool ExpandInlineAsm(CallInst *CI) const;
    614 
    615     ConstraintType getConstraintType(const std::string &Constraint) const;
    616 
    617     /// Examine constraint string and operand type and determine a weight value.
    618     /// The operand object must already have been set up with the operand type.
    619     virtual ConstraintWeight getSingleConstraintMatchWeight(
    620       AsmOperandInfo &info, const char *constraint) const;
    621 
    622     virtual const char *LowerXConstraint(EVT ConstraintVT) const;
    623 
    624     /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
    625     /// vector.  If it is invalid, don't add anything to Ops. If hasMemory is
    626     /// true it means one of the asm constraint of the inline asm instruction
    627     /// being processed is 'm'.
    628     virtual void LowerAsmOperandForConstraint(SDValue Op,
    629                                               std::string &Constraint,
    630                                               std::vector<SDValue> &Ops,
    631                                               SelectionDAG &DAG) const;
    632 
    633     /// getRegForInlineAsmConstraint - Given a physical register constraint
    634     /// (e.g. {edx}), return the register number and the register class for the
    635     /// register.  This should only be used for C_Register constraints.  On
    636     /// error, this returns a register number of 0.
    637     std::pair<unsigned, const TargetRegisterClass*>
    638       getRegForInlineAsmConstraint(const std::string &Constraint,
    639                                    EVT VT) const;
    640 
    641     /// isLegalAddressingMode - Return true if the addressing mode represented
    642     /// by AM is legal for this target, for a load/store of the specified type.
    643     virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
    644 
    645     /// isTruncateFree - Return true if it's free to truncate a value of
    646     /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
    647     /// register EAX to i16 by referencing its sub-register AX.
    648     virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
    649     virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
    650 
    651     /// isZExtFree - Return true if any actual instruction that defines a
    652     /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
    653     /// register. This does not necessarily include registers defined in
    654     /// unknown ways, such as incoming arguments, or copies from unknown
    655     /// virtual registers. Also, if isTruncateFree(Ty2, Ty1) is true, this
    656     /// does not necessarily apply to truncate instructions. e.g. on x86-64,
    657     /// all instructions that define 32-bit values implicit zero-extend the
    658     /// result out to 64 bits.
    659     virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
    660     virtual bool isZExtFree(EVT VT1, EVT VT2) const;
    661 
    662     /// isNarrowingProfitable - Return true if it's profitable to narrow
    663     /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
    664     /// from i32 to i8 but not from i32 to i16.
    665     virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
    666 
    667     /// isFPImmLegal - Returns true if the target can instruction select the
    668     /// specified FP immediate natively. If false, the legalizer will
    669     /// materialize the FP immediate as a load from a constant pool.
    670     virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
    671 
    672     /// isShuffleMaskLegal - Targets can use this to indicate that they only
    673     /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
    674     /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
    675     /// values are assumed to be legal.
    676     virtual bool isShuffleMaskLegal(const SmallVectorImpl<int> &Mask,
    677                                     EVT VT) const;
    678 
    679     /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
    680     /// used by Targets can use this to indicate if there is a suitable
    681     /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
    682     /// pool entry.
    683     virtual bool isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask,
    684                                         EVT VT) const;
    685 
    686     /// ShouldShrinkFPConstant - If true, then instruction selection should
    687     /// seek to shrink the FP constant of the specified type to a smaller type
    688     /// in order to save space and / or reduce runtime.
    689     virtual bool ShouldShrinkFPConstant(EVT VT) const {
    690       // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
    691       // expensive than a straight movsd. On the other hand, it's important to
    692       // shrink long double fp constant since fldt is very slow.
    693       return !X86ScalarSSEf64 || VT == MVT::f80;
    694     }
    695 
    696     const X86Subtarget* getSubtarget() const {
    697       return Subtarget;
    698     }
    699 
    700     /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
    701     /// computed in an SSE register, not on the X87 floating point stack.
    702     bool isScalarFPTypeInSSEReg(EVT VT) const {
    703       return (VT == MVT::f64 && X86ScalarSSEf64) || // f64 is when SSE2
    704       (VT == MVT::f32 && X86ScalarSSEf32);   // f32 is when SSE1
    705     }
    706 
    707     /// createFastISel - This method returns a target specific FastISel object,
    708     /// or null if the target does not support "fast" ISel.
    709     virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo) const;
    710 
    711     /// getStackCookieLocation - Return true if the target stores stack
    712     /// protector cookies at a fixed offset in some non-standard address
    713     /// space, and populates the address space and offset as
    714     /// appropriate.
    715     virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
    716 
    717     SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
    718                       SelectionDAG &DAG) const;
    719 
    720   protected:
    721     std::pair<const TargetRegisterClass*, uint8_t>
    722     findRepresentativeClass(EVT VT) const;
    723 
    724   private:
    725     /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
    726     /// make the right decision when generating code for different targets.
    727     const X86Subtarget *Subtarget;
    728     const X86RegisterInfo *RegInfo;
    729     const TargetData *TD;
    730 
    731     /// X86StackPtr - X86 physical register used as stack ptr.
    732     unsigned X86StackPtr;
    733 
    734     /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87
    735     /// floating point ops.
    736     /// When SSE is available, use it for f32 operations.
    737     /// When SSE2 is available, use it for f64 operations.
    738     bool X86ScalarSSEf32;
    739     bool X86ScalarSSEf64;
    740 
    741     /// LegalFPImmediates - A list of legal fp immediates.
    742     std::vector<APFloat> LegalFPImmediates;
    743 
    744     /// addLegalFPImmediate - Indicate that this x86 target can instruction
    745     /// select the specified FP immediate natively.
    746     void addLegalFPImmediate(const APFloat& Imm) {
    747       LegalFPImmediates.push_back(Imm);
    748     }
    749 
    750     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
    751                             CallingConv::ID CallConv, bool isVarArg,
    752                             const SmallVectorImpl<ISD::InputArg> &Ins,
    753                             DebugLoc dl, SelectionDAG &DAG,
    754                             SmallVectorImpl<SDValue> &InVals) const;
    755     SDValue LowerMemArgument(SDValue Chain,
    756                              CallingConv::ID CallConv,
    757                              const SmallVectorImpl<ISD::InputArg> &ArgInfo,
    758                              DebugLoc dl, SelectionDAG &DAG,
    759                              const CCValAssign &VA,  MachineFrameInfo *MFI,
    760                               unsigned i) const;
    761     SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
    762                              DebugLoc dl, SelectionDAG &DAG,
    763                              const CCValAssign &VA,
    764                              ISD::ArgFlagsTy Flags) const;
    765 
    766     // Call lowering helpers.
    767 
    768     /// IsEligibleForTailCallOptimization - Check whether the call is eligible
    769     /// for tail call optimization. Targets which want to do tail call
    770     /// optimization should implement this function.
    771     bool IsEligibleForTailCallOptimization(SDValue Callee,
    772                                            CallingConv::ID CalleeCC,
    773                                            bool isVarArg,
    774                                            bool isCalleeStructRet,
    775                                            bool isCallerStructRet,
    776                                     const SmallVectorImpl<ISD::OutputArg> &Outs,
    777                                     const SmallVectorImpl<SDValue> &OutVals,
    778                                     const SmallVectorImpl<ISD::InputArg> &Ins,
    779                                            SelectionDAG& DAG) const;
    780     bool IsCalleePop(bool isVarArg, CallingConv::ID CallConv) const;
    781     SDValue EmitTailCallLoadRetAddr(SelectionDAG &DAG, SDValue &OutRetAddr,
    782                                 SDValue Chain, bool IsTailCall, bool Is64Bit,
    783                                 int FPDiff, DebugLoc dl) const;
    784 
    785     unsigned GetAlignedArgumentStackSize(unsigned StackSize,
    786                                          SelectionDAG &DAG) const;
    787 
    788     std::pair<SDValue,SDValue> FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG,
    789                                                bool isSigned) const;
    790 
    791     SDValue LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
    792                                    SelectionDAG &DAG) const;
    793     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
    794     SDValue LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const;
    795     SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
    796     SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
    797     SDValue LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
    798     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
    799     SDValue LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG) const;
    800     SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
    801     SDValue LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
    802     SDValue LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const;
    803     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
    804     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
    805     SDValue LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl,
    806                                int64_t Offset, SelectionDAG &DAG) const;
    807     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
    808     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
    809     SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
    810     SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
    811     SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
    812     SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
    813     SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
    814     SDValue LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) const;
    815     SDValue LowerUINT_TO_FP_i32(SDValue Op, SelectionDAG &DAG) const;
    816     SDValue LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
    817     SDValue LowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
    818     SDValue LowerFABS(SDValue Op, SelectionDAG &DAG) const;
    819     SDValue LowerFNEG(SDValue Op, SelectionDAG &DAG) const;
    820     SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
    821     SDValue LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const;
    822     SDValue LowerToBT(SDValue And, ISD::CondCode CC,
    823                       DebugLoc dl, SelectionDAG &DAG) const;
    824     SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
    825     SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
    826     SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
    827     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
    828     SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
    829     SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
    830     SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
    831     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
    832     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
    833     SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
    834     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
    835     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
    836     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
    837     SDValue LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const;
    838     SDValue LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const;
    839     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
    840     SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
    841     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
    842     SDValue LowerCTLZ(SDValue Op, SelectionDAG &DAG) const;
    843     SDValue LowerCTTZ(SDValue Op, SelectionDAG &DAG) const;
    844     SDValue LowerADD(SDValue Op, SelectionDAG &DAG) const;
    845     SDValue LowerSUB(SDValue Op, SelectionDAG &DAG) const;
    846     SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
    847     SDValue LowerShift(SDValue Op, SelectionDAG &DAG) const;
    848     SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
    849 
    850     SDValue LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
    851     SDValue LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
    852     SDValue LowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
    853     SDValue LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const;
    854     SDValue LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const;
    855     SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
    856 
    857     // Utility functions to help LowerVECTOR_SHUFFLE
    858     SDValue LowerVECTOR_SHUFFLEv8i16(SDValue Op, SelectionDAG &DAG) const;
    859 
    860     virtual SDValue
    861       LowerFormalArguments(SDValue Chain,
    862                            CallingConv::ID CallConv, bool isVarArg,
    863                            const SmallVectorImpl<ISD::InputArg> &Ins,
    864                            DebugLoc dl, SelectionDAG &DAG,
    865                            SmallVectorImpl<SDValue> &InVals) const;
    866     virtual SDValue
    867       LowerCall(SDValue Chain, SDValue Callee,
    868                 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
    869                 const SmallVectorImpl<ISD::OutputArg> &Outs,
    870                 const SmallVectorImpl<SDValue> &OutVals,
    871                 const SmallVectorImpl<ISD::InputArg> &Ins,
    872                 DebugLoc dl, SelectionDAG &DAG,
    873                 SmallVectorImpl<SDValue> &InVals) const;
    874 
    875     virtual SDValue
    876       LowerReturn(SDValue Chain,
    877                   CallingConv::ID CallConv, bool isVarArg,
    878                   const SmallVectorImpl<ISD::OutputArg> &Outs,
    879                   const SmallVectorImpl<SDValue> &OutVals,
    880                   DebugLoc dl, SelectionDAG &DAG) const;
    881 
    882     virtual bool isUsedByReturnOnly(SDNode *N) const;
    883 
    884     virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
    885 
    886     virtual EVT
    887     getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT,
    888                              ISD::NodeType ExtendKind) const;
    889 
    890     virtual bool
    891     CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
    892 		   bool isVarArg,
    893 		   const SmallVectorImpl<ISD::OutputArg> &Outs,
    894 		   LLVMContext &Context) const;
    895 
    896     void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl<SDValue> &Results,
    897                                  SelectionDAG &DAG, unsigned NewOp) const;
    898 
    899     /// Utility function to emit string processing sse4.2 instructions
    900     /// that return in xmm0.
    901     /// This takes the instruction to expand, the associated machine basic
    902     /// block, the number of args, and whether or not the second arg is
    903     /// in memory or not.
    904     MachineBasicBlock *EmitPCMP(MachineInstr *BInstr, MachineBasicBlock *BB,
    905                                 unsigned argNum, bool inMem) const;
    906 
    907     /// Utility functions to emit monitor and mwait instructions. These
    908     /// need to make sure that the arguments to the intrinsic are in the
    909     /// correct registers.
    910     MachineBasicBlock *EmitMonitor(MachineInstr *MI,
    911                                    MachineBasicBlock *BB) const;
    912     MachineBasicBlock *EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const;
    913 
    914     /// Utility function to emit atomic bitwise operations (and, or, xor).
    915     /// It takes the bitwise instruction to expand, the associated machine basic
    916     /// block, and the associated X86 opcodes for reg/reg and reg/imm.
    917     MachineBasicBlock *EmitAtomicBitwiseWithCustomInserter(
    918                                                     MachineInstr *BInstr,
    919                                                     MachineBasicBlock *BB,
    920                                                     unsigned regOpc,
    921                                                     unsigned immOpc,
    922                                                     unsigned loadOpc,
    923                                                     unsigned cxchgOpc,
    924                                                     unsigned notOpc,
    925                                                     unsigned EAXreg,
    926                                                     TargetRegisterClass *RC,
    927                                                     bool invSrc = false) const;
    928 
    929     MachineBasicBlock *EmitAtomicBit6432WithCustomInserter(
    930                                                     MachineInstr *BInstr,
    931                                                     MachineBasicBlock *BB,
    932                                                     unsigned regOpcL,
    933                                                     unsigned regOpcH,
    934                                                     unsigned immOpcL,
    935                                                     unsigned immOpcH,
    936                                                     bool invSrc = false) const;
    937 
    938     /// Utility function to emit atomic min and max.  It takes the min/max
    939     /// instruction to expand, the associated basic block, and the associated
    940     /// cmov opcode for moving the min or max value.
    941     MachineBasicBlock *EmitAtomicMinMaxWithCustomInserter(MachineInstr *BInstr,
    942                                                           MachineBasicBlock *BB,
    943                                                         unsigned cmovOpc) const;
    944 
    945     // Utility function to emit the low-level va_arg code for X86-64.
    946     MachineBasicBlock *EmitVAARG64WithCustomInserter(
    947                        MachineInstr *MI,
    948                        MachineBasicBlock *MBB) const;
    949 
    950     /// Utility function to emit the xmm reg save portion of va_start.
    951     MachineBasicBlock *EmitVAStartSaveXMMRegsWithCustomInserter(
    952                                                    MachineInstr *BInstr,
    953                                                    MachineBasicBlock *BB) const;
    954 
    955     MachineBasicBlock *EmitLoweredSelect(MachineInstr *I,
    956                                          MachineBasicBlock *BB) const;
    957 
    958     MachineBasicBlock *EmitLoweredWinAlloca(MachineInstr *MI,
    959                                               MachineBasicBlock *BB) const;
    960 
    961     MachineBasicBlock *EmitLoweredSegAlloca(MachineInstr *MI,
    962                                             MachineBasicBlock *BB,
    963                                             bool Is64Bit) const;
    964 
    965     MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI,
    966                                           MachineBasicBlock *BB) const;
    967 
    968     MachineBasicBlock *emitLoweredTLSAddr(MachineInstr *MI,
    969                                           MachineBasicBlock *BB) const;
    970 
    971     /// Emit nodes that will be selected as "test Op0,Op0", or something
    972     /// equivalent, for use with the given x86 condition code.
    973     SDValue EmitTest(SDValue Op0, unsigned X86CC, SelectionDAG &DAG) const;
    974 
    975     /// Emit nodes that will be selected as "cmp Op0,Op1", or something
    976     /// equivalent, for use with the given x86 condition code.
    977     SDValue EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC,
    978                     SelectionDAG &DAG) const;
    979   };
    980 
    981   namespace X86 {
    982     FastISel *createFastISel(FunctionLoweringInfo &funcInfo);
    983   }
    984 }
    985 
    986 #endif    // X86ISELLOWERING_H
    987