1 /** @file 2 Header file of Serial port hardware definition. 3 4 Copyright (c) 2012 - 2014, Intel Corporation. All rights reserved.<BR> 5 6 This program and the accompanying materials are licensed and made available under 8 the terms and conditions of the BSD License that accompanies this distribution. 10 The full text of the license may be found at 12 http://opensource.org/licenses/bsd-license.php. 14 16 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, 18 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. 20 22 This software and associated documentation 24 (if any) is furnished under a license and may only be used or 25 copied in accordance with the terms of the license. Except as 26 permitted by such license, no part of this software or 27 documentation may be reproduced, stored in a retrieval system, or 28 transmitted in any form or by any means without the express written 29 consent of Intel Corporation. 30 31 Module Name: PlatformSerialPortLib.h 32 33 **/ 34 35 #ifndef _SIO_INIT_H_ 36 #define _SIO_INIT_H_ 37 38 #define WPCN381U_CONFIG_INDEX 0x2E 39 #define WPCN381U_CONFIG_DATA 0x2F 40 #define WPCN381U_CONFIG_INDEX1 0x164E 41 #define WPCN381U_CONFIG_DATA1 0x164F 42 #define WPCN381U_CHIP_ID 0xF4 43 #define WDCP376_CHIP_ID 0xF1 44 45 // 46 // SIO Logical Devices Numbers 47 // 48 #define WPCN381U_LDN_UART0 0x03 // LDN for Serial Port Controller 49 #define WPCN381U_LDN_UART1 0x02 // LDN for Parallel Port Controller 50 #define WPCN381U_LDN_PS2K 0x06 // LDN for PS2 Keyboard Controller 51 #define WPCN381U_LDN_PS2M 0x05 // LDN for PS2 Mouse Controller 52 #define WPCN381U_KB_BASE1_ADDRESS 0x60 // Base Address of KB controller 53 #define WPCN381U_KB_BASE2_ADDRESS 0x64 // Base Address of KB controller 54 #define SIO_KBC_CLOCK 0x01 // 0/1/2 - 8/12/16 MHz KBC Clock Source 55 #define WPCN381U_LDN_GPIO 0x07 // LDN for GPIO 56 57 // 58 // SIO Registers Layout 59 // 60 #define WPCN381U_LD_SEL_REGISTER 0x07 // Logical Device Select Register Address 61 #define WPCN381U_DEV_ID_REGISTER 0x20 // Device Identification Register Address 62 #define WPCN381U_ACTIVATE_REGISTER 0x30 // Device Identification Register Address 63 #define WPCN381U_BASE1_HI_REGISTER 0x60 // Device BaseAddres Register #1 MSB Address 64 #define WPCN381U_BASE1_LO_REGISTER 0x61 // Device BaseAddres Register #1 LSB Address 65 #define WPCN381U_BASE2_HI_REGISTER 0x62 // Device BaseAddres Register #1 MSB Address 66 #define WPCN381U_BASE2_LO_REGISTER 0x63 // Device Ba1eAddres Register #1 LSB Address 67 #define WPCN381U_IRQ1_REGISTER 0x70 // Device IRQ Register #1 Address 68 #define WPCN381U_IRQ2_REGISTER 0x71 // Device IRQ Register #2 Address 69 70 // 71 // SIO Activation Values 72 // 73 #define WPCN381U_ACTIVATE_VALUE 0x01 // Value to activate Device 74 #define WPCN381U_DEACTIVATE_VALUE 0x00 // Value to deactivate Device 75 76 // 77 // SIO GPIO 78 // 79 #define WPCN381U_GPIO_BASE_ADDRESS 0x0A20 // SIO GPIO Base Address 80 81 // 82 // SIO Serial Port Settings 83 // 84 #define WPCN381U_SERIAL_PORT0_BASE_ADDRESS 0x03F8 // Base Address of Serial Port 0 (COMA / UART0) 85 #define WPCN381U_SERIAL_PORT1_BASE_ADDRESS 0x02F8 // Base Address of Serial Port 1 (COMB / UART1) 86 87 #endif 88
