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Searched
defs:Writes
(Results
1 - 8
of
8
) sorted by null
/external/llvm/include/llvm/CodeGen/
MachineInstrBundle.h
157
///
Writes
- One of the operands
writes
the virtual register.
158
bool
Writes
;
/external/llvm/utils/TableGen/
CodeGenSchedule.h
45
/// or a sequence of
writes
on one operand.
109
///
Writes
and ReadDefs are empty. ProcIndices contains 0 for any processor.
118
/// provided InstrRW records for this class. ItinClassDef or
Writes
/Reads may
126
/// that mapped the itinerary class to the variant
Writes
or Reads.
132
IdxVec
Writes
;
148
return ItinClassDef == IC && makeArrayRef(
Writes
) == W &&
370
void findRWs(const RecVec &RWDefs, IdxVec &
Writes
, IdxVec &Reads) const;
382
unsigned findSchedClassIdx(Record *ItinClassDef, ArrayRef<unsigned>
Writes
,
432
void collectRWResources(ArrayRef<unsigned>
Writes
, ArrayRef<unsigned> Reads,
SubtargetEmitter.cpp
852
IdxVec
Writes
= SC.
Writes
;
866
Writes
.clear();
869
Writes
, Reads);
872
if (
Writes
.empty()) {
879
Writes
, Reads);
883
if (
Writes
.empty()) {
888
// Sum resources across all operand
writes
.
893
for (unsigned W :
Writes
) {
[
all
...]
/external/swiftshader/third_party/LLVM/lib/CodeGen/
InlineSpiller.cpp
864
// If the instruction also
writes
VirtReg.reg, it had better not require the
866
bool Reads,
Writes
;
868
tie(Reads,
Writes
) = MI->readsWritesVirtualRegister(VirtReg.reg, &Ops);
869
if (
Writes
) {
[
all
...]
RegisterCoalescer.cpp
[
all
...]
/external/llvm/lib/CodeGen/
RegisterCoalescer.cpp
[
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...]
MachinePipeliner.cpp
[
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...]
/prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/
winioctl.h
763
DWORD
Writes
;
[
all
...]
Completed in 217 milliseconds