1 /* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith (at) tungstengraphics.com> 30 */ 31 32 #define INTEL_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low)) 33 #define SET_FIELD(value, field) (((value) << field ## _SHIFT) & field ## _MASK) 34 #define GET_FIELD(word, field) (((word) & field ## _MASK) >> field ## _SHIFT) 35 36 #ifndef BRW_DEFINES_H 37 #define BRW_DEFINES_H 38 39 /* 3D state: 40 */ 41 #define PIPE_CONTROL_NOWRITE 0x00 42 #define PIPE_CONTROL_WRITEIMMEDIATE 0x01 43 #define PIPE_CONTROL_WRITEDEPTH 0x02 44 #define PIPE_CONTROL_WRITETIMESTAMP 0x03 45 46 #define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00 47 #define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01 48 49 #define CMD_3D_PRIM 0x7b00 /* 3DPRIMITIVE */ 50 /* DW0 */ 51 # define GEN4_3DPRIM_TOPOLOGY_TYPE_SHIFT 10 52 # define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 15) 53 # define GEN4_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 15) 54 /* DW1 */ 55 # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8) 56 # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 8) 57 58 #define _3DPRIM_POINTLIST 0x01 59 #define _3DPRIM_LINELIST 0x02 60 #define _3DPRIM_LINESTRIP 0x03 61 #define _3DPRIM_TRILIST 0x04 62 #define _3DPRIM_TRISTRIP 0x05 63 #define _3DPRIM_TRIFAN 0x06 64 #define _3DPRIM_QUADLIST 0x07 65 #define _3DPRIM_QUADSTRIP 0x08 66 #define _3DPRIM_LINELIST_ADJ 0x09 67 #define _3DPRIM_LINESTRIP_ADJ 0x0A 68 #define _3DPRIM_TRILIST_ADJ 0x0B 69 #define _3DPRIM_TRISTRIP_ADJ 0x0C 70 #define _3DPRIM_TRISTRIP_REVERSE 0x0D 71 #define _3DPRIM_POLYGON 0x0E 72 #define _3DPRIM_RECTLIST 0x0F 73 #define _3DPRIM_LINELOOP 0x10 74 #define _3DPRIM_POINTLIST_BF 0x11 75 #define _3DPRIM_LINESTRIP_CONT 0x12 76 #define _3DPRIM_LINESTRIP_BF 0x13 77 #define _3DPRIM_LINESTRIP_CONT_BF 0x14 78 #define _3DPRIM_TRIFAN_NOSTIPPLE 0x15 79 80 #define BRW_ANISORATIO_2 0 81 #define BRW_ANISORATIO_4 1 82 #define BRW_ANISORATIO_6 2 83 #define BRW_ANISORATIO_8 3 84 #define BRW_ANISORATIO_10 4 85 #define BRW_ANISORATIO_12 5 86 #define BRW_ANISORATIO_14 6 87 #define BRW_ANISORATIO_16 7 88 89 #define BRW_BLENDFACTOR_ONE 0x1 90 #define BRW_BLENDFACTOR_SRC_COLOR 0x2 91 #define BRW_BLENDFACTOR_SRC_ALPHA 0x3 92 #define BRW_BLENDFACTOR_DST_ALPHA 0x4 93 #define BRW_BLENDFACTOR_DST_COLOR 0x5 94 #define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6 95 #define BRW_BLENDFACTOR_CONST_COLOR 0x7 96 #define BRW_BLENDFACTOR_CONST_ALPHA 0x8 97 #define BRW_BLENDFACTOR_SRC1_COLOR 0x9 98 #define BRW_BLENDFACTOR_SRC1_ALPHA 0x0A 99 #define BRW_BLENDFACTOR_ZERO 0x11 100 #define BRW_BLENDFACTOR_INV_SRC_COLOR 0x12 101 #define BRW_BLENDFACTOR_INV_SRC_ALPHA 0x13 102 #define BRW_BLENDFACTOR_INV_DST_ALPHA 0x14 103 #define BRW_BLENDFACTOR_INV_DST_COLOR 0x15 104 #define BRW_BLENDFACTOR_INV_CONST_COLOR 0x17 105 #define BRW_BLENDFACTOR_INV_CONST_ALPHA 0x18 106 #define BRW_BLENDFACTOR_INV_SRC1_COLOR 0x19 107 #define BRW_BLENDFACTOR_INV_SRC1_ALPHA 0x1A 108 109 #define BRW_BLENDFUNCTION_ADD 0 110 #define BRW_BLENDFUNCTION_SUBTRACT 1 111 #define BRW_BLENDFUNCTION_REVERSE_SUBTRACT 2 112 #define BRW_BLENDFUNCTION_MIN 3 113 #define BRW_BLENDFUNCTION_MAX 4 114 115 #define BRW_ALPHATEST_FORMAT_UNORM8 0 116 #define BRW_ALPHATEST_FORMAT_FLOAT32 1 117 118 #define BRW_CHROMAKEY_KILL_ON_ANY_MATCH 0 119 #define BRW_CHROMAKEY_REPLACE_BLACK 1 120 121 #define BRW_CLIP_API_OGL 0 122 #define BRW_CLIP_API_DX 1 123 124 #define BRW_CLIPMODE_NORMAL 0 125 #define BRW_CLIPMODE_CLIP_ALL 1 126 #define BRW_CLIPMODE_CLIP_NON_REJECTED 2 127 #define BRW_CLIPMODE_REJECT_ALL 3 128 #define BRW_CLIPMODE_ACCEPT_ALL 4 129 #define BRW_CLIPMODE_KERNEL_CLIP 5 130 131 #define BRW_CLIP_NDCSPACE 0 132 #define BRW_CLIP_SCREENSPACE 1 133 134 #define BRW_COMPAREFUNCTION_ALWAYS 0 135 #define BRW_COMPAREFUNCTION_NEVER 1 136 #define BRW_COMPAREFUNCTION_LESS 2 137 #define BRW_COMPAREFUNCTION_EQUAL 3 138 #define BRW_COMPAREFUNCTION_LEQUAL 4 139 #define BRW_COMPAREFUNCTION_GREATER 5 140 #define BRW_COMPAREFUNCTION_NOTEQUAL 6 141 #define BRW_COMPAREFUNCTION_GEQUAL 7 142 143 #define BRW_COVERAGE_PIXELS_HALF 0 144 #define BRW_COVERAGE_PIXELS_1 1 145 #define BRW_COVERAGE_PIXELS_2 2 146 #define BRW_COVERAGE_PIXELS_4 3 147 148 #define BRW_CULLMODE_BOTH 0 149 #define BRW_CULLMODE_NONE 1 150 #define BRW_CULLMODE_FRONT 2 151 #define BRW_CULLMODE_BACK 3 152 153 #define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM 0 154 #define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT 1 155 156 #define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0 157 #define BRW_DEPTHFORMAT_D32_FLOAT 1 158 #define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2 159 #define BRW_DEPTHFORMAT_D24_UNORM_X8_UINT 3 /* GEN5 */ 160 #define BRW_DEPTHFORMAT_D16_UNORM 5 161 162 #define BRW_FLOATING_POINT_IEEE_754 0 163 #define BRW_FLOATING_POINT_NON_IEEE_754 1 164 165 #define BRW_FRONTWINDING_CW 0 166 #define BRW_FRONTWINDING_CCW 1 167 168 #define BRW_SPRITE_POINT_ENABLE 16 169 170 #define BRW_CUT_INDEX_ENABLE (1 << 10) 171 172 #define BRW_INDEX_BYTE 0 173 #define BRW_INDEX_WORD 1 174 #define BRW_INDEX_DWORD 2 175 176 #define BRW_LOGICOPFUNCTION_CLEAR 0 177 #define BRW_LOGICOPFUNCTION_NOR 1 178 #define BRW_LOGICOPFUNCTION_AND_INVERTED 2 179 #define BRW_LOGICOPFUNCTION_COPY_INVERTED 3 180 #define BRW_LOGICOPFUNCTION_AND_REVERSE 4 181 #define BRW_LOGICOPFUNCTION_INVERT 5 182 #define BRW_LOGICOPFUNCTION_XOR 6 183 #define BRW_LOGICOPFUNCTION_NAND 7 184 #define BRW_LOGICOPFUNCTION_AND 8 185 #define BRW_LOGICOPFUNCTION_EQUIV 9 186 #define BRW_LOGICOPFUNCTION_NOOP 10 187 #define BRW_LOGICOPFUNCTION_OR_INVERTED 11 188 #define BRW_LOGICOPFUNCTION_COPY 12 189 #define BRW_LOGICOPFUNCTION_OR_REVERSE 13 190 #define BRW_LOGICOPFUNCTION_OR 14 191 #define BRW_LOGICOPFUNCTION_SET 15 192 193 #define BRW_MAPFILTER_NEAREST 0x0 194 #define BRW_MAPFILTER_LINEAR 0x1 195 #define BRW_MAPFILTER_ANISOTROPIC 0x2 196 197 #define BRW_MIPFILTER_NONE 0 198 #define BRW_MIPFILTER_NEAREST 1 199 #define BRW_MIPFILTER_LINEAR 3 200 201 #define BRW_ADDRESS_ROUNDING_ENABLE_U_MAG 0x20 202 #define BRW_ADDRESS_ROUNDING_ENABLE_U_MIN 0x10 203 #define BRW_ADDRESS_ROUNDING_ENABLE_V_MAG 0x08 204 #define BRW_ADDRESS_ROUNDING_ENABLE_V_MIN 0x04 205 #define BRW_ADDRESS_ROUNDING_ENABLE_R_MAG 0x02 206 #define BRW_ADDRESS_ROUNDING_ENABLE_R_MIN 0x01 207 208 #define BRW_POLYGON_FRONT_FACING 0 209 #define BRW_POLYGON_BACK_FACING 1 210 211 #define BRW_PREFILTER_ALWAYS 0x0 212 #define BRW_PREFILTER_NEVER 0x1 213 #define BRW_PREFILTER_LESS 0x2 214 #define BRW_PREFILTER_EQUAL 0x3 215 #define BRW_PREFILTER_LEQUAL 0x4 216 #define BRW_PREFILTER_GREATER 0x5 217 #define BRW_PREFILTER_NOTEQUAL 0x6 218 #define BRW_PREFILTER_GEQUAL 0x7 219 220 #define BRW_PROVOKING_VERTEX_0 0 221 #define BRW_PROVOKING_VERTEX_1 1 222 #define BRW_PROVOKING_VERTEX_2 2 223 224 #define BRW_RASTRULE_UPPER_LEFT 0 225 #define BRW_RASTRULE_UPPER_RIGHT 1 226 /* These are listed as "Reserved, but not seen as useful" 227 * in Intel documentation (page 212, "Point Rasterization Rule", 228 * section 7.4 "SF Pipeline State Summary", of document 229 * "Intel 965 Express Chipset Family and Intel G35 Express 230 * Chipset Graphics Controller Programmer's Reference Manual, 231 * Volume 2: 3D/Media", Revision 1.0b as of January 2008, 232 * available at 233 * http://intellinuxgraphics.org/documentation.html 234 * at the time of this writing). 235 * 236 * These appear to be supported on at least some 237 * i965-family devices, and the BRW_RASTRULE_LOWER_RIGHT 238 * is useful when using OpenGL to render to a FBO 239 * (which has the pixel coordinate Y orientation inverted 240 * with respect to the normal OpenGL pixel coordinate system). 241 */ 242 #define BRW_RASTRULE_LOWER_LEFT 2 243 #define BRW_RASTRULE_LOWER_RIGHT 3 244 245 #define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0 246 #define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1 247 #define BRW_RENDERTARGET_CLAMPRANGE_FORMAT 2 248 249 #define BRW_STENCILOP_KEEP 0 250 #define BRW_STENCILOP_ZERO 1 251 #define BRW_STENCILOP_REPLACE 2 252 #define BRW_STENCILOP_INCRSAT 3 253 #define BRW_STENCILOP_DECRSAT 4 254 #define BRW_STENCILOP_INCR 5 255 #define BRW_STENCILOP_DECR 6 256 #define BRW_STENCILOP_INVERT 7 257 258 /* Surface state DW0 */ 259 #define BRW_SURFACE_RC_READ_WRITE (1 << 8) 260 #define BRW_SURFACE_MIPLAYOUT_SHIFT 10 261 #define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0 262 #define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1 263 #define BRW_SURFACE_CUBEFACE_ENABLES 0x3f 264 #define BRW_SURFACE_BLEND_ENABLED (1 << 13) 265 #define BRW_SURFACE_WRITEDISABLE_B_SHIFT 14 266 #define BRW_SURFACE_WRITEDISABLE_G_SHIFT 15 267 #define BRW_SURFACE_WRITEDISABLE_R_SHIFT 16 268 #define BRW_SURFACE_WRITEDISABLE_A_SHIFT 17 269 270 #define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000 271 #define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001 272 #define BRW_SURFACEFORMAT_R32G32B32A32_UINT 0x002 273 #define BRW_SURFACEFORMAT_R32G32B32A32_UNORM 0x003 274 #define BRW_SURFACEFORMAT_R32G32B32A32_SNORM 0x004 275 #define BRW_SURFACEFORMAT_R64G64_FLOAT 0x005 276 #define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006 277 #define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007 278 #define BRW_SURFACEFORMAT_R32G32B32A32_USCALED 0x008 279 #define BRW_SURFACEFORMAT_R32G32B32_FLOAT 0x040 280 #define BRW_SURFACEFORMAT_R32G32B32_SINT 0x041 281 #define BRW_SURFACEFORMAT_R32G32B32_UINT 0x042 282 #define BRW_SURFACEFORMAT_R32G32B32_UNORM 0x043 283 #define BRW_SURFACEFORMAT_R32G32B32_SNORM 0x044 284 #define BRW_SURFACEFORMAT_R32G32B32_SSCALED 0x045 285 #define BRW_SURFACEFORMAT_R32G32B32_USCALED 0x046 286 #define BRW_SURFACEFORMAT_R16G16B16A16_UNORM 0x080 287 #define BRW_SURFACEFORMAT_R16G16B16A16_SNORM 0x081 288 #define BRW_SURFACEFORMAT_R16G16B16A16_SINT 0x082 289 #define BRW_SURFACEFORMAT_R16G16B16A16_UINT 0x083 290 #define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084 291 #define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085 292 #define BRW_SURFACEFORMAT_R32G32_SINT 0x086 293 #define BRW_SURFACEFORMAT_R32G32_UINT 0x087 294 #define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088 295 #define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089 296 #define BRW_SURFACEFORMAT_L32A32_FLOAT 0x08A 297 #define BRW_SURFACEFORMAT_R32G32_UNORM 0x08B 298 #define BRW_SURFACEFORMAT_R32G32_SNORM 0x08C 299 #define BRW_SURFACEFORMAT_R64_FLOAT 0x08D 300 #define BRW_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E 301 #define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F 302 #define BRW_SURFACEFORMAT_A32X32_FLOAT 0x090 303 #define BRW_SURFACEFORMAT_L32X32_FLOAT 0x091 304 #define BRW_SURFACEFORMAT_I32X32_FLOAT 0x092 305 #define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093 306 #define BRW_SURFACEFORMAT_R16G16B16A16_USCALED 0x094 307 #define BRW_SURFACEFORMAT_R32G32_SSCALED 0x095 308 #define BRW_SURFACEFORMAT_R32G32_USCALED 0x096 309 #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0 310 #define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1 311 #define BRW_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2 312 #define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3 313 #define BRW_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4 314 #define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5 315 #define BRW_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7 316 #define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8 317 #define BRW_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9 318 #define BRW_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA 319 #define BRW_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB 320 #define BRW_SURFACEFORMAT_R16G16_UNORM 0x0CC 321 #define BRW_SURFACEFORMAT_R16G16_SNORM 0x0CD 322 #define BRW_SURFACEFORMAT_R16G16_SINT 0x0CE 323 #define BRW_SURFACEFORMAT_R16G16_UINT 0x0CF 324 #define BRW_SURFACEFORMAT_R16G16_FLOAT 0x0D0 325 #define BRW_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1 326 #define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2 327 #define BRW_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3 328 #define BRW_SURFACEFORMAT_R32_SINT 0x0D6 329 #define BRW_SURFACEFORMAT_R32_UINT 0x0D7 330 #define BRW_SURFACEFORMAT_R32_FLOAT 0x0D8 331 #define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9 332 #define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA 333 #define BRW_SURFACEFORMAT_L16A16_UNORM 0x0DF 334 #define BRW_SURFACEFORMAT_I24X8_UNORM 0x0E0 335 #define BRW_SURFACEFORMAT_L24X8_UNORM 0x0E1 336 #define BRW_SURFACEFORMAT_A24X8_UNORM 0x0E2 337 #define BRW_SURFACEFORMAT_I32_FLOAT 0x0E3 338 #define BRW_SURFACEFORMAT_L32_FLOAT 0x0E4 339 #define BRW_SURFACEFORMAT_A32_FLOAT 0x0E5 340 #define BRW_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9 341 #define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA 342 #define BRW_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB 343 #define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC 344 #define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED 345 #define BRW_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE 346 #define BRW_SURFACEFORMAT_L16A16_FLOAT 0x0F0 347 #define BRW_SURFACEFORMAT_R32_UNORM 0x0F1 348 #define BRW_SURFACEFORMAT_R32_SNORM 0x0F2 349 #define BRW_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3 350 #define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4 351 #define BRW_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5 352 #define BRW_SURFACEFORMAT_R16G16_SSCALED 0x0F6 353 #define BRW_SURFACEFORMAT_R16G16_USCALED 0x0F7 354 #define BRW_SURFACEFORMAT_R32_SSCALED 0x0F8 355 #define BRW_SURFACEFORMAT_R32_USCALED 0x0F9 356 #define BRW_SURFACEFORMAT_B5G6R5_UNORM 0x100 357 #define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101 358 #define BRW_SURFACEFORMAT_B5G5R5A1_UNORM 0x102 359 #define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103 360 #define BRW_SURFACEFORMAT_B4G4R4A4_UNORM 0x104 361 #define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105 362 #define BRW_SURFACEFORMAT_R8G8_UNORM 0x106 363 #define BRW_SURFACEFORMAT_R8G8_SNORM 0x107 364 #define BRW_SURFACEFORMAT_R8G8_SINT 0x108 365 #define BRW_SURFACEFORMAT_R8G8_UINT 0x109 366 #define BRW_SURFACEFORMAT_R16_UNORM 0x10A 367 #define BRW_SURFACEFORMAT_R16_SNORM 0x10B 368 #define BRW_SURFACEFORMAT_R16_SINT 0x10C 369 #define BRW_SURFACEFORMAT_R16_UINT 0x10D 370 #define BRW_SURFACEFORMAT_R16_FLOAT 0x10E 371 #define BRW_SURFACEFORMAT_I16_UNORM 0x111 372 #define BRW_SURFACEFORMAT_L16_UNORM 0x112 373 #define BRW_SURFACEFORMAT_A16_UNORM 0x113 374 #define BRW_SURFACEFORMAT_L8A8_UNORM 0x114 375 #define BRW_SURFACEFORMAT_I16_FLOAT 0x115 376 #define BRW_SURFACEFORMAT_L16_FLOAT 0x116 377 #define BRW_SURFACEFORMAT_A16_FLOAT 0x117 378 #define BRW_SURFACEFORMAT_L8A8_UNORM_SRGB 0x118 379 #define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119 380 #define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A 381 #define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B 382 #define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C 383 #define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D 384 #define BRW_SURFACEFORMAT_R16_SSCALED 0x11E 385 #define BRW_SURFACEFORMAT_R16_USCALED 0x11F 386 #define BRW_SURFACEFORMAT_R8_UNORM 0x140 387 #define BRW_SURFACEFORMAT_R8_SNORM 0x141 388 #define BRW_SURFACEFORMAT_R8_SINT 0x142 389 #define BRW_SURFACEFORMAT_R8_UINT 0x143 390 #define BRW_SURFACEFORMAT_A8_UNORM 0x144 391 #define BRW_SURFACEFORMAT_I8_UNORM 0x145 392 #define BRW_SURFACEFORMAT_L8_UNORM 0x146 393 #define BRW_SURFACEFORMAT_P4A4_UNORM 0x147 394 #define BRW_SURFACEFORMAT_A4P4_UNORM 0x148 395 #define BRW_SURFACEFORMAT_R8_SSCALED 0x149 396 #define BRW_SURFACEFORMAT_R8_USCALED 0x14A 397 #define BRW_SURFACEFORMAT_L8_UNORM_SRGB 0x14C 398 #define BRW_SURFACEFORMAT_DXT1_RGB_SRGB 0x180 399 #define BRW_SURFACEFORMAT_R1_UINT 0x181 400 #define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182 401 #define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183 402 #define BRW_SURFACEFORMAT_BC1_UNORM 0x186 403 #define BRW_SURFACEFORMAT_BC2_UNORM 0x187 404 #define BRW_SURFACEFORMAT_BC3_UNORM 0x188 405 #define BRW_SURFACEFORMAT_BC4_UNORM 0x189 406 #define BRW_SURFACEFORMAT_BC5_UNORM 0x18A 407 #define BRW_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B 408 #define BRW_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C 409 #define BRW_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D 410 #define BRW_SURFACEFORMAT_MONO8 0x18E 411 #define BRW_SURFACEFORMAT_YCRCB_SWAPUV 0x18F 412 #define BRW_SURFACEFORMAT_YCRCB_SWAPY 0x190 413 #define BRW_SURFACEFORMAT_DXT1_RGB 0x191 414 #define BRW_SURFACEFORMAT_FXT1 0x192 415 #define BRW_SURFACEFORMAT_R8G8B8_UNORM 0x193 416 #define BRW_SURFACEFORMAT_R8G8B8_SNORM 0x194 417 #define BRW_SURFACEFORMAT_R8G8B8_SSCALED 0x195 418 #define BRW_SURFACEFORMAT_R8G8B8_USCALED 0x196 419 #define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197 420 #define BRW_SURFACEFORMAT_R64G64B64_FLOAT 0x198 421 #define BRW_SURFACEFORMAT_BC4_SNORM 0x199 422 #define BRW_SURFACEFORMAT_BC5_SNORM 0x19A 423 #define BRW_SURFACEFORMAT_R16G16B16_UNORM 0x19C 424 #define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D 425 #define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E 426 #define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F 427 #define BRW_SURFACE_FORMAT_SHIFT 18 428 #define BRW_SURFACE_FORMAT_MASK INTEL_MASK(26, 18) 429 430 #define BRW_SURFACERETURNFORMAT_FLOAT32 0 431 #define BRW_SURFACERETURNFORMAT_S1 1 432 433 #define BRW_SURFACE_TYPE_SHIFT 29 434 #define BRW_SURFACE_TYPE_MASK INTEL_MASK(31, 29) 435 #define BRW_SURFACE_1D 0 436 #define BRW_SURFACE_2D 1 437 #define BRW_SURFACE_3D 2 438 #define BRW_SURFACE_CUBE 3 439 #define BRW_SURFACE_BUFFER 4 440 #define BRW_SURFACE_NULL 7 441 442 #define GEN7_SURFACE_ARYSPC_FULL 0 443 #define GEN7_SURFACE_ARYSPC_LOD0 1 444 445 /* Surface state DW2 */ 446 #define BRW_SURFACE_HEIGHT_SHIFT 19 447 #define BRW_SURFACE_HEIGHT_MASK INTEL_MASK(31, 19) 448 #define BRW_SURFACE_WIDTH_SHIFT 6 449 #define BRW_SURFACE_WIDTH_MASK INTEL_MASK(18, 6) 450 #define BRW_SURFACE_LOD_SHIFT 2 451 #define BRW_SURFACE_LOD_MASK INTEL_MASK(5, 2) 452 453 /* Surface state DW3 */ 454 #define BRW_SURFACE_DEPTH_SHIFT 21 455 #define BRW_SURFACE_DEPTH_MASK INTEL_MASK(31, 21) 456 #define BRW_SURFACE_PITCH_SHIFT 3 457 #define BRW_SURFACE_PITCH_MASK INTEL_MASK(19, 3) 458 #define BRW_SURFACE_TILED (1 << 1) 459 #define BRW_SURFACE_TILED_Y (1 << 0) 460 461 /* Surface state DW4 */ 462 #define BRW_SURFACE_MIN_LOD_SHIFT 28 463 #define BRW_SURFACE_MIN_LOD_MASK INTEL_MASK(31, 28) 464 #define BRW_SURFACE_MULTISAMPLECOUNT_1 (0 << 4) 465 #define BRW_SURFACE_MULTISAMPLECOUNT_4 (2 << 4) 466 #define GEN7_SURFACE_MULTISAMPLECOUNT_1 0 467 #define GEN7_SURFACE_MULTISAMPLECOUNT_4 2 468 #define GEN7_SURFACE_MULTISAMPLECOUNT_8 3 469 #define GEN7_SURFACE_MSFMT_MSS 0 470 #define GEN7_SURFACE_MSFMT_DEPTH_STENCIL 1 471 472 /* Surface state DW5 */ 473 #define BRW_SURFACE_X_OFFSET_SHIFT 25 474 #define BRW_SURFACE_X_OFFSET_MASK INTEL_MASK(31, 25) 475 #define BRW_SURFACE_VERTICAL_ALIGN_ENABLE (1 << 24) 476 #define BRW_SURFACE_Y_OFFSET_SHIFT 20 477 #define BRW_SURFACE_Y_OFFSET_MASK INTEL_MASK(23, 20) 478 479 /* Surface state DW7 */ 480 #define HSW_SCS_ZERO 0 481 #define HSW_SCS_ONE 1 482 #define HSW_SCS_RED 4 483 #define HSW_SCS_GREEN 5 484 #define HSW_SCS_BLUE 6 485 #define HSW_SCS_ALPHA 7 486 487 #define BRW_TEXCOORDMODE_WRAP 0 488 #define BRW_TEXCOORDMODE_MIRROR 1 489 #define BRW_TEXCOORDMODE_CLAMP 2 490 #define BRW_TEXCOORDMODE_CUBE 3 491 #define BRW_TEXCOORDMODE_CLAMP_BORDER 4 492 #define BRW_TEXCOORDMODE_MIRROR_ONCE 5 493 494 #define BRW_THREAD_PRIORITY_NORMAL 0 495 #define BRW_THREAD_PRIORITY_HIGH 1 496 497 #define BRW_TILEWALK_XMAJOR 0 498 #define BRW_TILEWALK_YMAJOR 1 499 500 #define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS 0 501 #define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS 1 502 503 /* Execution Unit (EU) defines 504 */ 505 506 #define BRW_ALIGN_1 0 507 #define BRW_ALIGN_16 1 508 509 #define BRW_ADDRESS_DIRECT 0 510 #define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1 511 512 #define BRW_CHANNEL_X 0 513 #define BRW_CHANNEL_Y 1 514 #define BRW_CHANNEL_Z 2 515 #define BRW_CHANNEL_W 3 516 517 enum brw_compression { 518 BRW_COMPRESSION_NONE = 0, 519 BRW_COMPRESSION_2NDHALF = 1, 520 BRW_COMPRESSION_COMPRESSED = 2, 521 }; 522 523 #define GEN6_COMPRESSION_1Q 0 524 #define GEN6_COMPRESSION_2Q 1 525 #define GEN6_COMPRESSION_3Q 2 526 #define GEN6_COMPRESSION_4Q 3 527 #define GEN6_COMPRESSION_1H 0 528 #define GEN6_COMPRESSION_2H 2 529 530 #define BRW_CONDITIONAL_NONE 0 531 #define BRW_CONDITIONAL_Z 1 532 #define BRW_CONDITIONAL_NZ 2 533 #define BRW_CONDITIONAL_EQ 1 /* Z */ 534 #define BRW_CONDITIONAL_NEQ 2 /* NZ */ 535 #define BRW_CONDITIONAL_G 3 536 #define BRW_CONDITIONAL_GE 4 537 #define BRW_CONDITIONAL_L 5 538 #define BRW_CONDITIONAL_LE 6 539 #define BRW_CONDITIONAL_R 7 540 #define BRW_CONDITIONAL_O 8 541 #define BRW_CONDITIONAL_U 9 542 543 #define BRW_DEBUG_NONE 0 544 #define BRW_DEBUG_BREAKPOINT 1 545 546 #define BRW_DEPENDENCY_NORMAL 0 547 #define BRW_DEPENDENCY_NOTCLEARED 1 548 #define BRW_DEPENDENCY_NOTCHECKED 2 549 #define BRW_DEPENDENCY_DISABLE 3 550 551 #define BRW_EXECUTE_1 0 552 #define BRW_EXECUTE_2 1 553 #define BRW_EXECUTE_4 2 554 #define BRW_EXECUTE_8 3 555 #define BRW_EXECUTE_16 4 556 #define BRW_EXECUTE_32 5 557 558 #define BRW_HORIZONTAL_STRIDE_0 0 559 #define BRW_HORIZONTAL_STRIDE_1 1 560 #define BRW_HORIZONTAL_STRIDE_2 2 561 #define BRW_HORIZONTAL_STRIDE_4 3 562 563 #define BRW_INSTRUCTION_NORMAL 0 564 #define BRW_INSTRUCTION_SATURATE 1 565 566 #define BRW_MASK_ENABLE 0 567 #define BRW_MASK_DISABLE 1 568 569 /** @{ 570 * 571 * Gen6 has replaced "mask enable/disable" with WECtrl, which is 572 * effectively the same but much simpler to think about. Now, there 573 * are two contributors ANDed together to whether channels are 574 * executed: The predication on the instruction, and the channel write 575 * enable. 576 */ 577 /** 578 * This is the default value. It means that a channel's write enable is set 579 * if the per-channel IP is pointing at this instruction. 580 */ 581 #define BRW_WE_NORMAL 0 582 /** 583 * This is used like BRW_MASK_DISABLE, and causes all channels to have 584 * their write enable set. Note that predication still contributes to 585 * whether the channel actually gets written. 586 */ 587 #define BRW_WE_ALL 1 588 /** @} */ 589 590 enum opcode { 591 /* These are the actual hardware opcodes. */ 592 BRW_OPCODE_MOV = 1, 593 BRW_OPCODE_SEL = 2, 594 BRW_OPCODE_NOT = 4, 595 BRW_OPCODE_AND = 5, 596 BRW_OPCODE_OR = 6, 597 BRW_OPCODE_XOR = 7, 598 BRW_OPCODE_SHR = 8, 599 BRW_OPCODE_SHL = 9, 600 BRW_OPCODE_RSR = 10, 601 BRW_OPCODE_RSL = 11, 602 BRW_OPCODE_ASR = 12, 603 BRW_OPCODE_CMP = 16, 604 BRW_OPCODE_CMPN = 17, 605 BRW_OPCODE_JMPI = 32, 606 BRW_OPCODE_IF = 34, 607 BRW_OPCODE_IFF = 35, 608 BRW_OPCODE_ELSE = 36, 609 BRW_OPCODE_ENDIF = 37, 610 BRW_OPCODE_DO = 38, 611 BRW_OPCODE_WHILE = 39, 612 BRW_OPCODE_BREAK = 40, 613 BRW_OPCODE_CONTINUE = 41, 614 BRW_OPCODE_HALT = 42, 615 BRW_OPCODE_MSAVE = 44, 616 BRW_OPCODE_MRESTORE = 45, 617 BRW_OPCODE_PUSH = 46, 618 BRW_OPCODE_POP = 47, 619 BRW_OPCODE_WAIT = 48, 620 BRW_OPCODE_SEND = 49, 621 BRW_OPCODE_SENDC = 50, 622 BRW_OPCODE_MATH = 56, 623 BRW_OPCODE_ADD = 64, 624 BRW_OPCODE_MUL = 65, 625 BRW_OPCODE_AVG = 66, 626 BRW_OPCODE_FRC = 67, 627 BRW_OPCODE_RNDU = 68, 628 BRW_OPCODE_RNDD = 69, 629 BRW_OPCODE_RNDE = 70, 630 BRW_OPCODE_RNDZ = 71, 631 BRW_OPCODE_MAC = 72, 632 BRW_OPCODE_MACH = 73, 633 BRW_OPCODE_LZD = 74, 634 BRW_OPCODE_SAD2 = 80, 635 BRW_OPCODE_SADA2 = 81, 636 BRW_OPCODE_DP4 = 84, 637 BRW_OPCODE_DPH = 85, 638 BRW_OPCODE_DP3 = 86, 639 BRW_OPCODE_DP2 = 87, 640 BRW_OPCODE_DPA2 = 88, 641 BRW_OPCODE_LINE = 89, 642 BRW_OPCODE_PLN = 90, 643 BRW_OPCODE_MAD = 91, 644 BRW_OPCODE_NOP = 126, 645 646 /* These are compiler backend opcodes that get translated into other 647 * instructions. 648 */ 649 FS_OPCODE_FB_WRITE = 128, 650 SHADER_OPCODE_RCP, 651 SHADER_OPCODE_RSQ, 652 SHADER_OPCODE_SQRT, 653 SHADER_OPCODE_EXP2, 654 SHADER_OPCODE_LOG2, 655 SHADER_OPCODE_POW, 656 SHADER_OPCODE_INT_QUOTIENT, 657 SHADER_OPCODE_INT_REMAINDER, 658 SHADER_OPCODE_SIN, 659 SHADER_OPCODE_COS, 660 661 SHADER_OPCODE_TEX, 662 SHADER_OPCODE_TXD, 663 SHADER_OPCODE_TXF, 664 SHADER_OPCODE_TXL, 665 SHADER_OPCODE_TXS, 666 FS_OPCODE_TXB, 667 668 FS_OPCODE_DDX, 669 FS_OPCODE_DDY, 670 FS_OPCODE_PIXEL_X, 671 FS_OPCODE_PIXEL_Y, 672 FS_OPCODE_CINTERP, 673 FS_OPCODE_LINTERP, 674 FS_OPCODE_DISCARD, 675 FS_OPCODE_SPILL, 676 FS_OPCODE_UNSPILL, 677 FS_OPCODE_PULL_CONSTANT_LOAD, 678 FS_OPCODE_MOV_DISPATCH_TO_FLAGS, 679 680 VS_OPCODE_URB_WRITE, 681 VS_OPCODE_SCRATCH_READ, 682 VS_OPCODE_SCRATCH_WRITE, 683 VS_OPCODE_PULL_CONSTANT_LOAD, 684 }; 685 686 #define BRW_PREDICATE_NONE 0 687 #define BRW_PREDICATE_NORMAL 1 688 #define BRW_PREDICATE_ALIGN1_ANYV 2 689 #define BRW_PREDICATE_ALIGN1_ALLV 3 690 #define BRW_PREDICATE_ALIGN1_ANY2H 4 691 #define BRW_PREDICATE_ALIGN1_ALL2H 5 692 #define BRW_PREDICATE_ALIGN1_ANY4H 6 693 #define BRW_PREDICATE_ALIGN1_ALL4H 7 694 #define BRW_PREDICATE_ALIGN1_ANY8H 8 695 #define BRW_PREDICATE_ALIGN1_ALL8H 9 696 #define BRW_PREDICATE_ALIGN1_ANY16H 10 697 #define BRW_PREDICATE_ALIGN1_ALL16H 11 698 #define BRW_PREDICATE_ALIGN16_REPLICATE_X 2 699 #define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3 700 #define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4 701 #define BRW_PREDICATE_ALIGN16_REPLICATE_W 5 702 #define BRW_PREDICATE_ALIGN16_ANY4H 6 703 #define BRW_PREDICATE_ALIGN16_ALL4H 7 704 705 #define BRW_ARCHITECTURE_REGISTER_FILE 0 706 #define BRW_GENERAL_REGISTER_FILE 1 707 #define BRW_MESSAGE_REGISTER_FILE 2 708 #define BRW_IMMEDIATE_VALUE 3 709 710 #define BRW_REGISTER_TYPE_UD 0 711 #define BRW_REGISTER_TYPE_D 1 712 #define BRW_REGISTER_TYPE_UW 2 713 #define BRW_REGISTER_TYPE_W 3 714 #define BRW_REGISTER_TYPE_UB 4 715 #define BRW_REGISTER_TYPE_B 5 716 #define BRW_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */ 717 #define BRW_REGISTER_TYPE_HF 6 718 #define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */ 719 #define BRW_REGISTER_TYPE_F 7 720 721 #define BRW_ARF_NULL 0x00 722 #define BRW_ARF_ADDRESS 0x10 723 #define BRW_ARF_ACCUMULATOR 0x20 724 #define BRW_ARF_FLAG 0x30 725 #define BRW_ARF_MASK 0x40 726 #define BRW_ARF_MASK_STACK 0x50 727 #define BRW_ARF_MASK_STACK_DEPTH 0x60 728 #define BRW_ARF_STATE 0x70 729 #define BRW_ARF_CONTROL 0x80 730 #define BRW_ARF_NOTIFICATION_COUNT 0x90 731 #define BRW_ARF_IP 0xA0 732 733 #define BRW_MRF_COMPR4 (1 << 7) 734 735 #define BRW_AMASK 0 736 #define BRW_IMASK 1 737 #define BRW_LMASK 2 738 #define BRW_CMASK 3 739 740 741 742 #define BRW_THREAD_NORMAL 0 743 #define BRW_THREAD_ATOMIC 1 744 #define BRW_THREAD_SWITCH 2 745 746 #define BRW_VERTICAL_STRIDE_0 0 747 #define BRW_VERTICAL_STRIDE_1 1 748 #define BRW_VERTICAL_STRIDE_2 2 749 #define BRW_VERTICAL_STRIDE_4 3 750 #define BRW_VERTICAL_STRIDE_8 4 751 #define BRW_VERTICAL_STRIDE_16 5 752 #define BRW_VERTICAL_STRIDE_32 6 753 #define BRW_VERTICAL_STRIDE_64 7 754 #define BRW_VERTICAL_STRIDE_128 8 755 #define BRW_VERTICAL_STRIDE_256 9 756 #define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF 757 758 #define BRW_WIDTH_1 0 759 #define BRW_WIDTH_2 1 760 #define BRW_WIDTH_4 2 761 #define BRW_WIDTH_8 3 762 #define BRW_WIDTH_16 4 763 764 #define BRW_STATELESS_BUFFER_BOUNDARY_1K 0 765 #define BRW_STATELESS_BUFFER_BOUNDARY_2K 1 766 #define BRW_STATELESS_BUFFER_BOUNDARY_4K 2 767 #define BRW_STATELESS_BUFFER_BOUNDARY_8K 3 768 #define BRW_STATELESS_BUFFER_BOUNDARY_16K 4 769 #define BRW_STATELESS_BUFFER_BOUNDARY_32K 5 770 #define BRW_STATELESS_BUFFER_BOUNDARY_64K 6 771 #define BRW_STATELESS_BUFFER_BOUNDARY_128K 7 772 #define BRW_STATELESS_BUFFER_BOUNDARY_256K 8 773 #define BRW_STATELESS_BUFFER_BOUNDARY_512K 9 774 #define BRW_STATELESS_BUFFER_BOUNDARY_1M 10 775 #define BRW_STATELESS_BUFFER_BOUNDARY_2M 11 776 777 #define BRW_POLYGON_FACING_FRONT 0 778 #define BRW_POLYGON_FACING_BACK 1 779 780 /** 781 * Message target: Shared Function ID for where to SEND a message. 782 * 783 * These are enumerated in the ISA reference under "send - Send Message". 784 * In particular, see the following tables: 785 * - G45 PRM, Volume 4, Table 14-15 "Message Descriptor Definition" 786 * - Sandybridge PRM, Volume 4 Part 2, Table 8-16 "Extended Message Descriptor" 787 * - BSpec, Volume 1a (GPU Overview) / Graphics Processing Engine (GPE) / 788 * Overview / GPE Function IDs 789 */ 790 enum brw_message_target { 791 BRW_SFID_NULL = 0, 792 BRW_SFID_MATH = 1, /* Only valid on Gen4-5 */ 793 BRW_SFID_SAMPLER = 2, 794 BRW_SFID_MESSAGE_GATEWAY = 3, 795 BRW_SFID_DATAPORT_READ = 4, 796 BRW_SFID_DATAPORT_WRITE = 5, 797 BRW_SFID_URB = 6, 798 BRW_SFID_THREAD_SPAWNER = 7, 799 800 GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4, 801 GEN6_SFID_DATAPORT_RENDER_CACHE = 5, 802 GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9, 803 804 GEN7_SFID_DATAPORT_DATA_CACHE = 10, 805 }; 806 807 #define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10 808 809 #define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0 810 #define BRW_SAMPLER_RETURN_FORMAT_UINT32 2 811 #define BRW_SAMPLER_RETURN_FORMAT_SINT32 3 812 813 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0 814 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0 815 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0 816 #define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1 817 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1 818 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1 819 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2 820 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2 821 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0 822 #define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2 823 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_BIAS_COMPARE 0 824 #define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD_COMPARE 1 825 #define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_LOD_COMPARE 1 826 #define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2 827 #define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2 828 #define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3 829 #define BRW_SAMPLER_MESSAGE_SIMD8_LD 3 830 #define BRW_SAMPLER_MESSAGE_SIMD16_LD 3 831 832 #define GEN5_SAMPLER_MESSAGE_SAMPLE 0 833 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS 1 834 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD 2 835 #define GEN5_SAMPLER_MESSAGE_SAMPLE_COMPARE 3 836 #define GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS 4 837 #define GEN5_SAMPLER_MESSAGE_SAMPLE_BIAS_COMPARE 5 838 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LOD_COMPARE 6 839 #define GEN5_SAMPLER_MESSAGE_SAMPLE_LD 7 840 #define GEN5_SAMPLER_MESSAGE_SAMPLE_RESINFO 10 841 #define HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE 20 842 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS 29 843 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS 30 844 #define GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS 31 845 846 /* for GEN5 only */ 847 #define BRW_SAMPLER_SIMD_MODE_SIMD4X2 0 848 #define BRW_SAMPLER_SIMD_MODE_SIMD8 1 849 #define BRW_SAMPLER_SIMD_MODE_SIMD16 2 850 #define BRW_SAMPLER_SIMD_MODE_SIMD32_64 3 851 852 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0 853 #define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1 854 #define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2 855 #define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3 856 #define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4 857 858 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0 859 #define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2 860 861 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2 862 #define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3 863 864 /* This one stays the same across generations. */ 865 #define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0 866 /* GEN4 */ 867 #define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1 868 #define BRW_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 2 869 #define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3 870 /* G45, GEN5 */ 871 #define G45_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 872 #define G45_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 873 #define G45_DATAPORT_READ_MESSAGE_AVC_LOOP_FILTER_READ 3 874 #define G45_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 875 #define G45_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 876 /* GEN6 */ 877 #define GEN6_DATAPORT_READ_MESSAGE_RENDER_UNORM_READ 1 878 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 2 879 #define GEN6_DATAPORT_READ_MESSAGE_MEDIA_BLOCK_READ 4 880 #define GEN6_DATAPORT_READ_MESSAGE_OWORD_UNALIGN_BLOCK_READ 5 881 #define GEN6_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 6 882 883 #define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0 884 #define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1 885 #define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2 886 887 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0 888 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1 889 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2 890 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3 891 #define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4 892 893 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0 894 #define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1 895 #define BRW_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 2 896 #define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3 897 #define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4 898 #define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5 899 #define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7 900 901 /* GEN6 */ 902 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_ATOMIC_WRITE 7 903 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 8 904 #define GEN6_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 9 905 #define GEN6_DATAPORT_WRITE_MESSAGE_MEDIA_BLOCK_WRITE 10 906 #define GEN6_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 11 907 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 12 908 #define GEN6_DATAPORT_WRITE_MESSAGE_STREAMED_VB_WRITE 13 909 #define GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_UNORM_WRITE 14 910 911 /* GEN7 */ 912 #define GEN7_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 10 913 914 #define BRW_MATH_FUNCTION_INV 1 915 #define BRW_MATH_FUNCTION_LOG 2 916 #define BRW_MATH_FUNCTION_EXP 3 917 #define BRW_MATH_FUNCTION_SQRT 4 918 #define BRW_MATH_FUNCTION_RSQ 5 919 #define BRW_MATH_FUNCTION_SIN 6 /* was 7 */ 920 #define BRW_MATH_FUNCTION_COS 7 /* was 8 */ 921 #define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */ 922 #define BRW_MATH_FUNCTION_TAN 9 /* gen4 */ 923 #define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */ 924 #define BRW_MATH_FUNCTION_POW 10 925 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11 926 #define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12 927 #define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13 928 929 #define BRW_MATH_INTEGER_UNSIGNED 0 930 #define BRW_MATH_INTEGER_SIGNED 1 931 932 #define BRW_MATH_PRECISION_FULL 0 933 #define BRW_MATH_PRECISION_PARTIAL 1 934 935 #define BRW_MATH_SATURATE_NONE 0 936 #define BRW_MATH_SATURATE_SATURATE 1 937 938 #define BRW_MATH_DATA_VECTOR 0 939 #define BRW_MATH_DATA_SCALAR 1 940 941 #define BRW_URB_OPCODE_WRITE 0 942 943 #define BRW_URB_SWIZZLE_NONE 0 944 #define BRW_URB_SWIZZLE_INTERLEAVE 1 945 #define BRW_URB_SWIZZLE_TRANSPOSE 2 946 947 #define BRW_SCRATCH_SPACE_SIZE_1K 0 948 #define BRW_SCRATCH_SPACE_SIZE_2K 1 949 #define BRW_SCRATCH_SPACE_SIZE_4K 2 950 #define BRW_SCRATCH_SPACE_SIZE_8K 3 951 #define BRW_SCRATCH_SPACE_SIZE_16K 4 952 #define BRW_SCRATCH_SPACE_SIZE_32K 5 953 #define BRW_SCRATCH_SPACE_SIZE_64K 6 954 #define BRW_SCRATCH_SPACE_SIZE_128K 7 955 #define BRW_SCRATCH_SPACE_SIZE_256K 8 956 #define BRW_SCRATCH_SPACE_SIZE_512K 9 957 #define BRW_SCRATCH_SPACE_SIZE_1M 10 958 #define BRW_SCRATCH_SPACE_SIZE_2M 11 959 960 961 962 963 #define CMD_URB_FENCE 0x6000 964 #define CMD_CS_URB_STATE 0x6001 965 #define CMD_CONST_BUFFER 0x6002 966 967 #define CMD_STATE_BASE_ADDRESS 0x6101 968 #define CMD_STATE_SIP 0x6102 969 #define CMD_PIPELINE_SELECT_965 0x6104 970 #define CMD_PIPELINE_SELECT_GM45 0x6904 971 972 #define _3DSTATE_PIPELINED_POINTERS 0x7800 973 #define _3DSTATE_BINDING_TABLE_POINTERS 0x7801 974 # define GEN6_BINDING_TABLE_MODIFY_VS (1 << 8) 975 # define GEN6_BINDING_TABLE_MODIFY_GS (1 << 9) 976 # define GEN6_BINDING_TABLE_MODIFY_PS (1 << 12) 977 978 #define _3DSTATE_BINDING_TABLE_POINTERS_VS 0x7826 /* GEN7+ */ 979 #define _3DSTATE_BINDING_TABLE_POINTERS_HS 0x7827 /* GEN7+ */ 980 #define _3DSTATE_BINDING_TABLE_POINTERS_DS 0x7828 /* GEN7+ */ 981 #define _3DSTATE_BINDING_TABLE_POINTERS_GS 0x7829 /* GEN7+ */ 982 #define _3DSTATE_BINDING_TABLE_POINTERS_PS 0x782A /* GEN7+ */ 983 984 #define _3DSTATE_SAMPLER_STATE_POINTERS 0x7802 /* GEN6+ */ 985 # define PS_SAMPLER_STATE_CHANGE (1 << 12) 986 # define GS_SAMPLER_STATE_CHANGE (1 << 9) 987 # define VS_SAMPLER_STATE_CHANGE (1 << 8) 988 /* DW1: VS */ 989 /* DW2: GS */ 990 /* DW3: PS */ 991 992 #define _3DSTATE_SAMPLER_STATE_POINTERS_VS 0x782B /* GEN7+ */ 993 #define _3DSTATE_SAMPLER_STATE_POINTERS_GS 0x782E /* GEN7+ */ 994 #define _3DSTATE_SAMPLER_STATE_POINTERS_PS 0x782F /* GEN7+ */ 995 996 #define _3DSTATE_VERTEX_BUFFERS 0x7808 997 # define BRW_VB0_INDEX_SHIFT 27 998 # define GEN6_VB0_INDEX_SHIFT 26 999 # define BRW_VB0_ACCESS_VERTEXDATA (0 << 26) 1000 # define BRW_VB0_ACCESS_INSTANCEDATA (1 << 26) 1001 # define GEN6_VB0_ACCESS_VERTEXDATA (0 << 20) 1002 # define GEN6_VB0_ACCESS_INSTANCEDATA (1 << 20) 1003 # define GEN7_VB0_ADDRESS_MODIFYENABLE (1 << 14) 1004 # define BRW_VB0_PITCH_SHIFT 0 1005 1006 #define _3DSTATE_VERTEX_ELEMENTS 0x7809 1007 # define BRW_VE0_INDEX_SHIFT 27 1008 # define GEN6_VE0_INDEX_SHIFT 26 1009 # define BRW_VE0_FORMAT_SHIFT 16 1010 # define BRW_VE0_VALID (1 << 26) 1011 # define GEN6_VE0_VALID (1 << 25) 1012 # define GEN6_VE0_EDGE_FLAG_ENABLE (1 << 15) 1013 # define BRW_VE0_SRC_OFFSET_SHIFT 0 1014 # define BRW_VE1_COMPONENT_NOSTORE 0 1015 # define BRW_VE1_COMPONENT_STORE_SRC 1 1016 # define BRW_VE1_COMPONENT_STORE_0 2 1017 # define BRW_VE1_COMPONENT_STORE_1_FLT 3 1018 # define BRW_VE1_COMPONENT_STORE_1_INT 4 1019 # define BRW_VE1_COMPONENT_STORE_VID 5 1020 # define BRW_VE1_COMPONENT_STORE_IID 6 1021 # define BRW_VE1_COMPONENT_STORE_PID 7 1022 # define BRW_VE1_COMPONENT_0_SHIFT 28 1023 # define BRW_VE1_COMPONENT_1_SHIFT 24 1024 # define BRW_VE1_COMPONENT_2_SHIFT 20 1025 # define BRW_VE1_COMPONENT_3_SHIFT 16 1026 # define BRW_VE1_DST_OFFSET_SHIFT 0 1027 1028 #define CMD_INDEX_BUFFER 0x780a 1029 #define GEN4_3DSTATE_VF_STATISTICS 0x780b 1030 #define GM45_3DSTATE_VF_STATISTICS 0x680b 1031 #define _3DSTATE_CC_STATE_POINTERS 0x780e /* GEN6+ */ 1032 #define _3DSTATE_BLEND_STATE_POINTERS 0x7824 /* GEN7+ */ 1033 #define _3DSTATE_DEPTH_STENCIL_STATE_POINTERS 0x7825 /* GEN7+ */ 1034 1035 #define _3DSTATE_URB 0x7805 /* GEN6 */ 1036 # define GEN6_URB_VS_SIZE_SHIFT 16 1037 # define GEN6_URB_VS_ENTRIES_SHIFT 0 1038 # define GEN6_URB_GS_ENTRIES_SHIFT 8 1039 # define GEN6_URB_GS_SIZE_SHIFT 0 1040 1041 #define _3DSTATE_VF 0x780c /* GEN7.5+ */ 1042 #define HSW_CUT_INDEX_ENABLE (1 << 8) 1043 1044 #define _3DSTATE_URB_VS 0x7830 /* GEN7+ */ 1045 #define _3DSTATE_URB_HS 0x7831 /* GEN7+ */ 1046 #define _3DSTATE_URB_DS 0x7832 /* GEN7+ */ 1047 #define _3DSTATE_URB_GS 0x7833 /* GEN7+ */ 1048 # define GEN7_URB_ENTRY_SIZE_SHIFT 16 1049 # define GEN7_URB_STARTING_ADDRESS_SHIFT 25 1050 1051 #define _3DSTATE_PUSH_CONSTANT_ALLOC_VS 0x7912 /* GEN7+ */ 1052 #define _3DSTATE_PUSH_CONSTANT_ALLOC_PS 0x7916 /* GEN7+ */ 1053 # define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16 1054 1055 #define _3DSTATE_VIEWPORT_STATE_POINTERS 0x780d /* GEN6+ */ 1056 # define GEN6_CC_VIEWPORT_MODIFY (1 << 12) 1057 # define GEN6_SF_VIEWPORT_MODIFY (1 << 11) 1058 # define GEN6_CLIP_VIEWPORT_MODIFY (1 << 10) 1059 1060 #define _3DSTATE_VIEWPORT_STATE_POINTERS_CC 0x7823 /* GEN7+ */ 1061 #define _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL 0x7821 /* GEN7+ */ 1062 1063 #define _3DSTATE_SCISSOR_STATE_POINTERS 0x780f /* GEN6+ */ 1064 1065 #define _3DSTATE_VS 0x7810 /* GEN6+ */ 1066 /* DW2 */ 1067 # define GEN6_VS_SPF_MODE (1 << 31) 1068 # define GEN6_VS_VECTOR_MASK_ENABLE (1 << 30) 1069 # define GEN6_VS_SAMPLER_COUNT_SHIFT 27 1070 # define GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 1071 # define GEN6_VS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) 1072 # define GEN6_VS_FLOATING_POINT_MODE_ALT (1 << 16) 1073 /* DW4 */ 1074 # define GEN6_VS_DISPATCH_START_GRF_SHIFT 20 1075 # define GEN6_VS_URB_READ_LENGTH_SHIFT 11 1076 # define GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT 4 1077 /* DW5 */ 1078 # define GEN6_VS_MAX_THREADS_SHIFT 25 1079 # define HSW_VS_MAX_THREADS_SHIFT 23 1080 # define GEN6_VS_STATISTICS_ENABLE (1 << 10) 1081 # define GEN6_VS_CACHE_DISABLE (1 << 1) 1082 # define GEN6_VS_ENABLE (1 << 0) 1083 1084 #define _3DSTATE_GS 0x7811 /* GEN6+ */ 1085 /* DW2 */ 1086 # define GEN6_GS_SPF_MODE (1 << 31) 1087 # define GEN6_GS_VECTOR_MASK_ENABLE (1 << 30) 1088 # define GEN6_GS_SAMPLER_COUNT_SHIFT 27 1089 # define GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 1090 # define GEN6_GS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) 1091 # define GEN6_GS_FLOATING_POINT_MODE_ALT (1 << 16) 1092 /* DW4 */ 1093 # define GEN6_GS_URB_READ_LENGTH_SHIFT 11 1094 # define GEN7_GS_INCLUDE_VERTEX_HANDLES (1 << 10) 1095 # define GEN6_GS_URB_ENTRY_READ_OFFSET_SHIFT 4 1096 # define GEN6_GS_DISPATCH_START_GRF_SHIFT 0 1097 /* DW5 */ 1098 # define GEN6_GS_MAX_THREADS_SHIFT 25 1099 # define GEN6_GS_STATISTICS_ENABLE (1 << 10) 1100 # define GEN6_GS_SO_STATISTICS_ENABLE (1 << 9) 1101 # define GEN6_GS_RENDERING_ENABLE (1 << 8) 1102 # define GEN7_GS_ENABLE (1 << 0) 1103 /* DW6 */ 1104 # define GEN6_GS_REORDER (1 << 30) 1105 # define GEN6_GS_DISCARD_ADJACENCY (1 << 29) 1106 # define GEN6_GS_SVBI_PAYLOAD_ENABLE (1 << 28) 1107 # define GEN6_GS_SVBI_POSTINCREMENT_ENABLE (1 << 27) 1108 # define GEN6_GS_SVBI_POSTINCREMENT_VALUE_SHIFT 16 1109 # define GEN6_GS_SVBI_POSTINCREMENT_VALUE_MASK INTEL_MASK(25, 16) 1110 # define GEN6_GS_ENABLE (1 << 15) 1111 1112 # define BRW_GS_EDGE_INDICATOR_0 (1 << 8) 1113 # define BRW_GS_EDGE_INDICATOR_1 (1 << 9) 1114 1115 #define _3DSTATE_HS 0x781B /* GEN7+ */ 1116 #define _3DSTATE_TE 0x781C /* GEN7+ */ 1117 #define _3DSTATE_DS 0x781D /* GEN7+ */ 1118 1119 #define _3DSTATE_CLIP 0x7812 /* GEN6+ */ 1120 /* DW1 */ 1121 # define GEN7_CLIP_WINDING_CW (0 << 20) 1122 # define GEN7_CLIP_WINDING_CCW (1 << 20) 1123 # define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_8 (0 << 19) 1124 # define GEN7_CLIP_VERTEX_SUBPIXEL_PRECISION_4 (1 << 19) 1125 # define GEN7_CLIP_EARLY_CULL (1 << 18) 1126 # define GEN7_CLIP_CULLMODE_BOTH (0 << 16) 1127 # define GEN7_CLIP_CULLMODE_NONE (1 << 16) 1128 # define GEN7_CLIP_CULLMODE_FRONT (2 << 16) 1129 # define GEN7_CLIP_CULLMODE_BACK (3 << 16) 1130 # define GEN6_CLIP_STATISTICS_ENABLE (1 << 10) 1131 /** 1132 * Just does cheap culling based on the clip distance. Bits must be 1133 * disjoint with USER_CLIP_CLIP_DISTANCE bits. 1134 */ 1135 # define GEN6_USER_CLIP_CULL_DISTANCES_SHIFT 0 1136 /* DW2 */ 1137 # define GEN6_CLIP_ENABLE (1 << 31) 1138 # define GEN6_CLIP_API_OGL (0 << 30) 1139 # define GEN6_CLIP_API_D3D (1 << 30) 1140 # define GEN6_CLIP_XY_TEST (1 << 28) 1141 # define GEN6_CLIP_Z_TEST (1 << 27) 1142 # define GEN6_CLIP_GB_TEST (1 << 26) 1143 /** 8-bit field of which user clip distances to clip aganist. */ 1144 # define GEN6_USER_CLIP_CLIP_DISTANCES_SHIFT 16 1145 # define GEN6_CLIP_MODE_NORMAL (0 << 13) 1146 # define GEN6_CLIP_MODE_REJECT_ALL (3 << 13) 1147 # define GEN6_CLIP_MODE_ACCEPT_ALL (4 << 13) 1148 # define GEN6_CLIP_PERSPECTIVE_DIVIDE_DISABLE (1 << 9) 1149 # define GEN6_CLIP_NON_PERSPECTIVE_BARYCENTRIC_ENABLE (1 << 8) 1150 # define GEN6_CLIP_TRI_PROVOKE_SHIFT 4 1151 # define GEN6_CLIP_LINE_PROVOKE_SHIFT 2 1152 # define GEN6_CLIP_TRIFAN_PROVOKE_SHIFT 0 1153 /* DW3 */ 1154 # define GEN6_CLIP_MIN_POINT_WIDTH_SHIFT 17 1155 # define GEN6_CLIP_MAX_POINT_WIDTH_SHIFT 6 1156 # define GEN6_CLIP_FORCE_ZERO_RTAINDEX (1 << 5) 1157 1158 #define _3DSTATE_SF 0x7813 /* GEN6+ */ 1159 /* DW1 (for gen6) */ 1160 # define GEN6_SF_NUM_OUTPUTS_SHIFT 22 1161 # define GEN6_SF_SWIZZLE_ENABLE (1 << 21) 1162 # define GEN6_SF_POINT_SPRITE_UPPERLEFT (0 << 20) 1163 # define GEN6_SF_POINT_SPRITE_LOWERLEFT (1 << 20) 1164 # define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT 11 1165 # define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT 4 1166 /* DW2 */ 1167 # define GEN6_SF_LEGACY_GLOBAL_DEPTH_BIAS (1 << 11) 1168 # define GEN6_SF_STATISTICS_ENABLE (1 << 10) 1169 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_SOLID (1 << 9) 1170 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_WIREFRAME (1 << 8) 1171 # define GEN6_SF_GLOBAL_DEPTH_OFFSET_POINT (1 << 7) 1172 # define GEN6_SF_FRONT_SOLID (0 << 5) 1173 # define GEN6_SF_FRONT_WIREFRAME (1 << 5) 1174 # define GEN6_SF_FRONT_POINT (2 << 5) 1175 # define GEN6_SF_BACK_SOLID (0 << 3) 1176 # define GEN6_SF_BACK_WIREFRAME (1 << 3) 1177 # define GEN6_SF_BACK_POINT (2 << 3) 1178 # define GEN6_SF_VIEWPORT_TRANSFORM_ENABLE (1 << 1) 1179 # define GEN6_SF_WINDING_CCW (1 << 0) 1180 /* DW3 */ 1181 # define GEN6_SF_LINE_AA_ENABLE (1 << 31) 1182 # define GEN6_SF_CULL_BOTH (0 << 29) 1183 # define GEN6_SF_CULL_NONE (1 << 29) 1184 # define GEN6_SF_CULL_FRONT (2 << 29) 1185 # define GEN6_SF_CULL_BACK (3 << 29) 1186 # define GEN6_SF_LINE_WIDTH_SHIFT 18 /* U3.7 */ 1187 # define GEN6_SF_LINE_END_CAP_WIDTH_0_5 (0 << 16) 1188 # define GEN6_SF_LINE_END_CAP_WIDTH_1_0 (1 << 16) 1189 # define GEN6_SF_LINE_END_CAP_WIDTH_2_0 (2 << 16) 1190 # define GEN6_SF_LINE_END_CAP_WIDTH_4_0 (3 << 16) 1191 # define GEN6_SF_SCISSOR_ENABLE (1 << 11) 1192 # define GEN6_SF_MSRAST_OFF_PIXEL (0 << 8) 1193 # define GEN6_SF_MSRAST_OFF_PATTERN (1 << 8) 1194 # define GEN6_SF_MSRAST_ON_PIXEL (2 << 8) 1195 # define GEN6_SF_MSRAST_ON_PATTERN (3 << 8) 1196 /* DW4 */ 1197 # define GEN6_SF_TRI_PROVOKE_SHIFT 29 1198 # define GEN6_SF_LINE_PROVOKE_SHIFT 27 1199 # define GEN6_SF_TRIFAN_PROVOKE_SHIFT 25 1200 # define GEN6_SF_LINE_AA_MODE_MANHATTAN (0 << 14) 1201 # define GEN6_SF_LINE_AA_MODE_TRUE (1 << 14) 1202 # define GEN6_SF_VERTEX_SUBPIXEL_8BITS (0 << 12) 1203 # define GEN6_SF_VERTEX_SUBPIXEL_4BITS (1 << 12) 1204 # define GEN6_SF_USE_STATE_POINT_WIDTH (1 << 11) 1205 # define GEN6_SF_POINT_WIDTH_SHIFT 0 /* U8.3 */ 1206 /* DW5: depth offset constant */ 1207 /* DW6: depth offset scale */ 1208 /* DW7: depth offset clamp */ 1209 /* DW8 */ 1210 # define ATTRIBUTE_1_OVERRIDE_W (1 << 31) 1211 # define ATTRIBUTE_1_OVERRIDE_Z (1 << 30) 1212 # define ATTRIBUTE_1_OVERRIDE_Y (1 << 29) 1213 # define ATTRIBUTE_1_OVERRIDE_X (1 << 28) 1214 # define ATTRIBUTE_1_CONST_SOURCE_SHIFT 25 1215 # define ATTRIBUTE_1_SWIZZLE_SHIFT 22 1216 # define ATTRIBUTE_1_SOURCE_SHIFT 16 1217 # define ATTRIBUTE_0_OVERRIDE_W (1 << 15) 1218 # define ATTRIBUTE_0_OVERRIDE_Z (1 << 14) 1219 # define ATTRIBUTE_0_OVERRIDE_Y (1 << 13) 1220 # define ATTRIBUTE_0_OVERRIDE_X (1 << 12) 1221 # define ATTRIBUTE_0_CONST_SOURCE_SHIFT 9 1222 # define ATTRIBUTE_0_SWIZZLE_SHIFT 6 1223 # define ATTRIBUTE_0_SOURCE_SHIFT 0 1224 1225 # define ATTRIBUTE_SWIZZLE_INPUTATTR 0 1226 # define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING 1 1227 # define ATTRIBUTE_SWIZZLE_INPUTATTR_W 2 1228 # define ATTRIBUTE_SWIZZLE_INPUTATTR_FACING_W 3 1229 # define ATTRIBUTE_SWIZZLE_SHIFT 6 1230 1231 /* DW16: Point sprite texture coordinate enables */ 1232 /* DW17: Constant interpolation enables */ 1233 /* DW18: attr 0-7 wrap shortest enables */ 1234 /* DW19: attr 8-16 wrap shortest enables */ 1235 1236 /* On GEN7, many fields of 3DSTATE_SF were split out into a new command: 1237 * 3DSTATE_SBE. The remaining fields live in different DWords, but retain 1238 * the same bit-offset. The only new field: 1239 */ 1240 /* GEN7/DW1: */ 1241 # define GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT 12 1242 /* GEN7/DW2: */ 1243 # define HSW_SF_LINE_STIPPLE_ENABLE 14 1244 1245 #define _3DSTATE_SBE 0x781F /* GEN7+ */ 1246 /* DW1 */ 1247 # define GEN7_SBE_SWIZZLE_CONTROL_MODE (1 << 28) 1248 # define GEN7_SBE_NUM_OUTPUTS_SHIFT 22 1249 # define GEN7_SBE_SWIZZLE_ENABLE (1 << 21) 1250 # define GEN7_SBE_POINT_SPRITE_LOWERLEFT (1 << 20) 1251 # define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11 1252 # define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT 4 1253 /* DW2-9: Attribute setup (same as DW8-15 of gen6 _3DSTATE_SF) */ 1254 /* DW10: Point sprite texture coordinate enables */ 1255 /* DW11: Constant interpolation enables */ 1256 /* DW12: attr 0-7 wrap shortest enables */ 1257 /* DW13: attr 8-16 wrap shortest enables */ 1258 1259 enum brw_wm_barycentric_interp_mode { 1260 BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC = 0, 1261 BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC = 1, 1262 BRW_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC = 2, 1263 BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC = 3, 1264 BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC = 4, 1265 BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC = 5, 1266 BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT = 6 1267 }; 1268 #define BRW_WM_NONPERSPECTIVE_BARYCENTRIC_BITS \ 1269 ((1 << BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC) | \ 1270 (1 << BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC) | \ 1271 (1 << BRW_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC)) 1272 1273 #define _3DSTATE_WM 0x7814 /* GEN6+ */ 1274 /* DW1: kernel pointer */ 1275 /* DW2 */ 1276 # define GEN6_WM_SPF_MODE (1 << 31) 1277 # define GEN6_WM_VECTOR_MASK_ENABLE (1 << 30) 1278 # define GEN6_WM_SAMPLER_COUNT_SHIFT 27 1279 # define GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 1280 # define GEN6_WM_FLOATING_POINT_MODE_IEEE_754 (0 << 16) 1281 # define GEN6_WM_FLOATING_POINT_MODE_ALT (1 << 16) 1282 /* DW3: scratch space */ 1283 /* DW4 */ 1284 # define GEN6_WM_STATISTICS_ENABLE (1 << 31) 1285 # define GEN6_WM_DEPTH_CLEAR (1 << 30) 1286 # define GEN6_WM_DEPTH_RESOLVE (1 << 28) 1287 # define GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27) 1288 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_0 16 1289 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_1 8 1290 # define GEN6_WM_DISPATCH_START_GRF_SHIFT_2 0 1291 /* DW5 */ 1292 # define GEN6_WM_MAX_THREADS_SHIFT 25 1293 # define GEN6_WM_KILL_ENABLE (1 << 22) 1294 # define GEN6_WM_COMPUTED_DEPTH (1 << 21) 1295 # define GEN6_WM_USES_SOURCE_DEPTH (1 << 20) 1296 # define GEN6_WM_DISPATCH_ENABLE (1 << 19) 1297 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 16) 1298 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 16) 1299 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 16) 1300 # define GEN6_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 16) 1301 # define GEN6_WM_LINE_AA_WIDTH_0_5 (0 << 14) 1302 # define GEN6_WM_LINE_AA_WIDTH_1_0 (1 << 14) 1303 # define GEN6_WM_LINE_AA_WIDTH_2_0 (2 << 14) 1304 # define GEN6_WM_LINE_AA_WIDTH_4_0 (3 << 14) 1305 # define GEN6_WM_POLYGON_STIPPLE_ENABLE (1 << 13) 1306 # define GEN6_WM_LINE_STIPPLE_ENABLE (1 << 11) 1307 # define GEN6_WM_OMASK_TO_RENDER_TARGET (1 << 9) 1308 # define GEN6_WM_USES_SOURCE_W (1 << 8) 1309 # define GEN6_WM_DUAL_SOURCE_BLEND_ENABLE (1 << 7) 1310 # define GEN6_WM_32_DISPATCH_ENABLE (1 << 2) 1311 # define GEN6_WM_16_DISPATCH_ENABLE (1 << 1) 1312 # define GEN6_WM_8_DISPATCH_ENABLE (1 << 0) 1313 /* DW6 */ 1314 # define GEN6_WM_NUM_SF_OUTPUTS_SHIFT 20 1315 # define GEN6_WM_POSOFFSET_NONE (0 << 18) 1316 # define GEN6_WM_POSOFFSET_CENTROID (2 << 18) 1317 # define GEN6_WM_POSOFFSET_SAMPLE (3 << 18) 1318 # define GEN6_WM_POSITION_ZW_PIXEL (0 << 16) 1319 # define GEN6_WM_POSITION_ZW_CENTROID (2 << 16) 1320 # define GEN6_WM_POSITION_ZW_SAMPLE (3 << 16) 1321 # define GEN6_WM_NONPERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 15) 1322 # define GEN6_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC (1 << 14) 1323 # define GEN6_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC (1 << 13) 1324 # define GEN6_WM_PERSPECTIVE_SAMPLE_BARYCENTRIC (1 << 12) 1325 # define GEN6_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11) 1326 # define GEN6_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10) 1327 # define GEN6_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT 10 1328 # define GEN6_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 9) 1329 # define GEN6_WM_MSRAST_OFF_PIXEL (0 << 1) 1330 # define GEN6_WM_MSRAST_OFF_PATTERN (1 << 1) 1331 # define GEN6_WM_MSRAST_ON_PIXEL (2 << 1) 1332 # define GEN6_WM_MSRAST_ON_PATTERN (3 << 1) 1333 # define GEN6_WM_MSDISPMODE_PERSAMPLE (0 << 0) 1334 # define GEN6_WM_MSDISPMODE_PERPIXEL (1 << 0) 1335 /* DW7: kernel 1 pointer */ 1336 /* DW8: kernel 2 pointer */ 1337 1338 #define _3DSTATE_CONSTANT_VS 0x7815 /* GEN6+ */ 1339 #define _3DSTATE_CONSTANT_GS 0x7816 /* GEN6+ */ 1340 #define _3DSTATE_CONSTANT_PS 0x7817 /* GEN6+ */ 1341 # define GEN6_CONSTANT_BUFFER_3_ENABLE (1 << 15) 1342 # define GEN6_CONSTANT_BUFFER_2_ENABLE (1 << 14) 1343 # define GEN6_CONSTANT_BUFFER_1_ENABLE (1 << 13) 1344 # define GEN6_CONSTANT_BUFFER_0_ENABLE (1 << 12) 1345 1346 #define _3DSTATE_CONSTANT_HS 0x7819 /* GEN7+ */ 1347 #define _3DSTATE_CONSTANT_DS 0x781A /* GEN7+ */ 1348 1349 #define _3DSTATE_STREAMOUT 0x781e /* GEN7+ */ 1350 /* DW1 */ 1351 # define SO_FUNCTION_ENABLE (1 << 31) 1352 # define SO_RENDERING_DISABLE (1 << 30) 1353 /* This selects which incoming rendering stream goes down the pipeline. The 1354 * rendering stream is 0 if not defined by special cases in the GS state. 1355 */ 1356 # define SO_RENDER_STREAM_SELECT_SHIFT 27 1357 # define SO_RENDER_STREAM_SELECT_MASK INTEL_MASK(28, 27) 1358 /* Controls reordering of TRISTRIP_* elements in stream output (not rendering). 1359 */ 1360 # define SO_REORDER_TRAILING (1 << 26) 1361 /* Controls SO_NUM_PRIMS_WRITTEN_* and SO_PRIM_STORAGE_* */ 1362 # define SO_STATISTICS_ENABLE (1 << 25) 1363 # define SO_BUFFER_ENABLE(n) (1 << (8 + (n))) 1364 /* DW2 */ 1365 # define SO_STREAM_3_VERTEX_READ_OFFSET_SHIFT 29 1366 # define SO_STREAM_3_VERTEX_READ_OFFSET_MASK INTEL_MASK(29, 29) 1367 # define SO_STREAM_3_VERTEX_READ_LENGTH_SHIFT 24 1368 # define SO_STREAM_3_VERTEX_READ_LENGTH_MASK INTEL_MASK(28, 24) 1369 # define SO_STREAM_2_VERTEX_READ_OFFSET_SHIFT 21 1370 # define SO_STREAM_2_VERTEX_READ_OFFSET_MASK INTEL_MASK(21, 21) 1371 # define SO_STREAM_2_VERTEX_READ_LENGTH_SHIFT 16 1372 # define SO_STREAM_2_VERTEX_READ_LENGTH_MASK INTEL_MASK(20, 16) 1373 # define SO_STREAM_1_VERTEX_READ_OFFSET_SHIFT 13 1374 # define SO_STREAM_1_VERTEX_READ_OFFSET_MASK INTEL_MASK(13, 13) 1375 # define SO_STREAM_1_VERTEX_READ_LENGTH_SHIFT 8 1376 # define SO_STREAM_1_VERTEX_READ_LENGTH_MASK INTEL_MASK(12, 8) 1377 # define SO_STREAM_0_VERTEX_READ_OFFSET_SHIFT 5 1378 # define SO_STREAM_0_VERTEX_READ_OFFSET_MASK INTEL_MASK(5, 5) 1379 # define SO_STREAM_0_VERTEX_READ_LENGTH_SHIFT 0 1380 # define SO_STREAM_0_VERTEX_READ_LENGTH_MASK INTEL_MASK(4, 0) 1381 1382 /* 3DSTATE_WM for Gen7 */ 1383 /* DW1 */ 1384 # define GEN7_WM_STATISTICS_ENABLE (1 << 31) 1385 # define GEN7_WM_DEPTH_CLEAR (1 << 30) 1386 # define GEN7_WM_DISPATCH_ENABLE (1 << 29) 1387 # define GEN7_WM_DEPTH_RESOLVE (1 << 28) 1388 # define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27) 1389 # define GEN7_WM_KILL_ENABLE (1 << 25) 1390 # define GEN7_WM_PSCDEPTH_OFF (0 << 23) 1391 # define GEN7_WM_PSCDEPTH_ON (1 << 23) 1392 # define GEN7_WM_PSCDEPTH_ON_GE (2 << 23) 1393 # define GEN7_WM_PSCDEPTH_ON_LE (3 << 23) 1394 # define GEN7_WM_USES_SOURCE_DEPTH (1 << 20) 1395 # define GEN7_WM_USES_SOURCE_W (1 << 19) 1396 # define GEN7_WM_POSITION_ZW_PIXEL (0 << 17) 1397 # define GEN7_WM_POSITION_ZW_CENTROID (2 << 17) 1398 # define GEN7_WM_POSITION_ZW_SAMPLE (3 << 17) 1399 # define GEN7_WM_BARYCENTRIC_INTERPOLATION_MODE_SHIFT 11 1400 # define GEN7_WM_USES_INPUT_COVERAGE_MASK (1 << 10) 1401 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5 (0 << 8) 1402 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_1_0 (1 << 8) 1403 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_2_0 (2 << 8) 1404 # define GEN7_WM_LINE_END_CAP_AA_WIDTH_4_0 (3 << 8) 1405 # define GEN7_WM_LINE_AA_WIDTH_0_5 (0 << 6) 1406 # define GEN7_WM_LINE_AA_WIDTH_1_0 (1 << 6) 1407 # define GEN7_WM_LINE_AA_WIDTH_2_0 (2 << 6) 1408 # define GEN7_WM_LINE_AA_WIDTH_4_0 (3 << 6) 1409 # define GEN7_WM_POLYGON_STIPPLE_ENABLE (1 << 4) 1410 # define GEN7_WM_LINE_STIPPLE_ENABLE (1 << 3) 1411 # define GEN7_WM_POINT_RASTRULE_UPPER_RIGHT (1 << 2) 1412 # define GEN7_WM_MSRAST_OFF_PIXEL (0 << 0) 1413 # define GEN7_WM_MSRAST_OFF_PATTERN (1 << 0) 1414 # define GEN7_WM_MSRAST_ON_PIXEL (2 << 0) 1415 # define GEN7_WM_MSRAST_ON_PATTERN (3 << 0) 1416 /* DW2 */ 1417 # define GEN7_WM_MSDISPMODE_PERSAMPLE (0 << 31) 1418 # define GEN7_WM_MSDISPMODE_PERPIXEL (1 << 31) 1419 1420 #define _3DSTATE_PS 0x7820 /* GEN7+ */ 1421 /* DW1: kernel pointer */ 1422 /* DW2 */ 1423 # define GEN7_PS_SPF_MODE (1 << 31) 1424 # define GEN7_PS_VECTOR_MASK_ENABLE (1 << 30) 1425 # define GEN7_PS_SAMPLER_COUNT_SHIFT 27 1426 # define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18 1427 # define GEN7_PS_FLOATING_POINT_MODE_IEEE_754 (0 << 16) 1428 # define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16) 1429 /* DW3: scratch space */ 1430 /* DW4 */ 1431 # define IVB_PS_MAX_THREADS_SHIFT 24 1432 # define HSW_PS_MAX_THREADS_SHIFT 23 1433 # define HSW_PS_SAMPLE_MASK_SHIFT 12 1434 # define HSW_PS_SAMPLE_MASK_MASK INTEL_MASK(19, 12) 1435 # define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11) 1436 # define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10) 1437 # define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9) 1438 # define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE (1 << 7) 1439 # define GEN7_PS_POSOFFSET_NONE (0 << 3) 1440 # define GEN7_PS_POSOFFSET_CENTROID (2 << 3) 1441 # define GEN7_PS_POSOFFSET_SAMPLE (3 << 3) 1442 # define GEN7_PS_32_DISPATCH_ENABLE (1 << 2) 1443 # define GEN7_PS_16_DISPATCH_ENABLE (1 << 1) 1444 # define GEN7_PS_8_DISPATCH_ENABLE (1 << 0) 1445 /* DW5 */ 1446 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_0 16 1447 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_1 8 1448 # define GEN7_PS_DISPATCH_START_GRF_SHIFT_2 0 1449 /* DW6: kernel 1 pointer */ 1450 /* DW7: kernel 2 pointer */ 1451 1452 #define _3DSTATE_SAMPLE_MASK 0x7818 /* GEN6+ */ 1453 1454 #define _3DSTATE_DRAWING_RECTANGLE 0x7900 1455 #define _3DSTATE_BLEND_CONSTANT_COLOR 0x7901 1456 #define _3DSTATE_CHROMA_KEY 0x7904 1457 #define _3DSTATE_DEPTH_BUFFER 0x7905 /* GEN4-6 */ 1458 #define _3DSTATE_POLY_STIPPLE_OFFSET 0x7906 1459 #define _3DSTATE_POLY_STIPPLE_PATTERN 0x7907 1460 #define _3DSTATE_LINE_STIPPLE_PATTERN 0x7908 1461 #define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x7909 1462 #define _3DSTATE_AA_LINE_PARAMETERS 0x790a /* G45+ */ 1463 1464 #define _3DSTATE_GS_SVB_INDEX 0x790b /* CTG+ */ 1465 /* DW1 */ 1466 # define SVB_INDEX_SHIFT 29 1467 # define SVB_LOAD_INTERNAL_VERTEX_COUNT (1 << 0) /* SNB+ */ 1468 /* DW2: SVB index */ 1469 /* DW3: SVB maximum index */ 1470 1471 #define _3DSTATE_MULTISAMPLE 0x790d /* GEN6+ */ 1472 /* DW1 */ 1473 # define MS_PIXEL_LOCATION_CENTER (0 << 4) 1474 # define MS_PIXEL_LOCATION_UPPER_LEFT (1 << 4) 1475 # define MS_NUMSAMPLES_1 (0 << 1) 1476 # define MS_NUMSAMPLES_4 (2 << 1) 1477 # define MS_NUMSAMPLES_8 (3 << 1) 1478 1479 #define _3DSTATE_STENCIL_BUFFER 0x790e /* ILK, SNB */ 1480 #define _3DSTATE_HIER_DEPTH_BUFFER 0x790f /* ILK, SNB */ 1481 1482 #define GEN7_3DSTATE_CLEAR_PARAMS 0x7804 1483 #define GEN7_3DSTATE_DEPTH_BUFFER 0x7805 1484 #define GEN7_3DSTATE_STENCIL_BUFFER 0x7806 1485 # define HSW_STENCIL_ENABLED (1 << 31) 1486 #define GEN7_3DSTATE_HIER_DEPTH_BUFFER 0x7807 1487 1488 #define _3DSTATE_CLEAR_PARAMS 0x7910 /* ILK, SNB */ 1489 # define GEN5_DEPTH_CLEAR_VALID (1 << 15) 1490 /* DW1: depth clear value */ 1491 /* DW2 */ 1492 # define GEN7_DEPTH_CLEAR_VALID (1 << 0) 1493 1494 #define _3DSTATE_SO_DECL_LIST 0x7917 /* GEN7+ */ 1495 /* DW1 */ 1496 # define SO_STREAM_TO_BUFFER_SELECTS_3_SHIFT 12 1497 # define SO_STREAM_TO_BUFFER_SELECTS_3_MASK INTEL_MASK(15, 12) 1498 # define SO_STREAM_TO_BUFFER_SELECTS_2_SHIFT 8 1499 # define SO_STREAM_TO_BUFFER_SELECTS_2_MASK INTEL_MASK(11, 8) 1500 # define SO_STREAM_TO_BUFFER_SELECTS_1_SHIFT 4 1501 # define SO_STREAM_TO_BUFFER_SELECTS_1_MASK INTEL_MASK(7, 4) 1502 # define SO_STREAM_TO_BUFFER_SELECTS_0_SHIFT 0 1503 # define SO_STREAM_TO_BUFFER_SELECTS_0_MASK INTEL_MASK(3, 0) 1504 /* DW2 */ 1505 # define SO_NUM_ENTRIES_3_SHIFT 24 1506 # define SO_NUM_ENTRIES_3_MASK INTEL_MASK(31, 24) 1507 # define SO_NUM_ENTRIES_2_SHIFT 16 1508 # define SO_NUM_ENTRIES_2_MASK INTEL_MASK(23, 16) 1509 # define SO_NUM_ENTRIES_1_SHIFT 8 1510 # define SO_NUM_ENTRIES_1_MASK INTEL_MASK(15, 8) 1511 # define SO_NUM_ENTRIES_0_SHIFT 0 1512 # define SO_NUM_ENTRIES_0_MASK INTEL_MASK(7, 0) 1513 1514 /* SO_DECL DW0 */ 1515 # define SO_DECL_OUTPUT_BUFFER_SLOT_SHIFT 12 1516 # define SO_DECL_OUTPUT_BUFFER_SLOT_MASK INTEL_MASK(13, 12) 1517 # define SO_DECL_HOLE_FLAG (1 << 11) 1518 # define SO_DECL_REGISTER_INDEX_SHIFT 4 1519 # define SO_DECL_REGISTER_INDEX_MASK INTEL_MASK(9, 4) 1520 # define SO_DECL_COMPONENT_MASK_SHIFT 0 1521 # define SO_DECL_COMPONENT_MASK_MASK INTEL_MASK(3, 0) 1522 1523 #define _3DSTATE_SO_BUFFER 0x7918 /* GEN7+ */ 1524 /* DW1 */ 1525 # define SO_BUFFER_INDEX_SHIFT 29 1526 # define SO_BUFFER_INDEX_MASK INTEL_MASK(30, 29) 1527 # define SO_BUFFER_PITCH_SHIFT 0 1528 # define SO_BUFFER_PITCH_MASK INTEL_MASK(11, 0) 1529 /* DW2: start address */ 1530 /* DW3: end address. */ 1531 1532 #define CMD_PIPE_CONTROL 0x7a00 1533 1534 #define CMD_MI_FLUSH 0x0200 1535 1536 1537 /* Bitfields for the URB_WRITE message, DW2 of message header: */ 1538 #define URB_WRITE_PRIM_END 0x1 1539 #define URB_WRITE_PRIM_START 0x2 1540 #define URB_WRITE_PRIM_TYPE_SHIFT 2 1541 1542 1543 /* Maximum number of entries that can be addressed using a binding table 1544 * pointer of type SURFTYPE_BUFFER 1545 */ 1546 #define BRW_MAX_NUM_BUFFER_ENTRIES (1 << 27) 1547 1548 #include "intel_chipset.h" 1549 1550 #endif 1551
