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      1 /*
      2  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
      3  *
      4  * Redistribution and use in source and binary forms, with or without
      5  * modification, are permitted provided that the following conditions are met:
      6  *
      7  * Redistributions of source code must retain the above copyright notice, this
      8  * list of conditions and the following disclaimer.
      9  *
     10  * Redistributions in binary form must reproduce the above copyright notice,
     11  * this list of conditions and the following disclaimer in the documentation
     12  * and/or other materials provided with the distribution.
     13  *
     14  * Neither the name of ARM nor the names of its contributors may be used
     15  * to endorse or promote products derived from this software without specific
     16  * prior written permission.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
     22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #include <platform_def.h>
     32 
     33 OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
     34 OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
     35 ENTRY(tsp_entrypoint)
     36 
     37 
     38 MEMORY {
     39     RAM (rwx): ORIGIN = TSP_SEC_MEM_BASE, LENGTH = TSP_SEC_MEM_SIZE
     40 }
     41 
     42 
     43 SECTIONS
     44 {
     45     . = BL32_BASE;
     46     ASSERT(. == ALIGN(4096),
     47            "BL32_BASE address is not aligned on a page boundary.")
     48 
     49     ro . : {
     50         __RO_START__ = .;
     51         *tsp_entrypoint.o(.text*)
     52         *(.text*)
     53         *(.rodata*)
     54         *(.vectors)
     55         __RO_END_UNALIGNED__ = .;
     56         /*
     57          * Memory page(s) mapped to this section will be marked as
     58          * read-only, executable.  No RW data from the next section must
     59          * creep in.  Ensure the rest of the current memory page is unused.
     60          */
     61         . = NEXT(4096);
     62         __RO_END__ = .;
     63     } >RAM
     64 
     65     .data . : {
     66         __DATA_START__ = .;
     67         *(.data*)
     68         __DATA_END__ = .;
     69     } >RAM
     70 
     71 #ifdef TSP_PROGBITS_LIMIT
     72     ASSERT(. <= TSP_PROGBITS_LIMIT, "TSP progbits has exceeded its limit.")
     73 #endif
     74 
     75     stacks (NOLOAD) : {
     76         __STACKS_START__ = .;
     77         *(tzfw_normal_stacks)
     78         __STACKS_END__ = .;
     79     } >RAM
     80 
     81     /*
     82      * The .bss section gets initialised to 0 at runtime.
     83      * Its base address must be 16-byte aligned.
     84      */
     85     .bss : ALIGN(16) {
     86         __BSS_START__ = .;
     87         *(SORT_BY_ALIGNMENT(.bss*))
     88         *(COMMON)
     89         __BSS_END__ = .;
     90     } >RAM
     91 
     92     /*
     93      * The xlat_table section is for full, aligned page tables (4K).
     94      * Removing them from .bss avoids forcing 4K alignment on
     95      * the .bss section and eliminates the unecessary zero init
     96      */
     97     xlat_table (NOLOAD) : {
     98         *(xlat_table)
     99     } >RAM
    100 
    101 #if USE_COHERENT_MEM
    102     /*
    103      * The base address of the coherent memory section must be page-aligned (4K)
    104      * to guarantee that the coherent data are stored on their own pages and
    105      * are not mixed with normal data.  This is required to set up the correct
    106      * memory attributes for the coherent data page tables.
    107      */
    108     coherent_ram (NOLOAD) : ALIGN(4096) {
    109         __COHERENT_RAM_START__ = .;
    110         *(tzfw_coherent_mem)
    111         __COHERENT_RAM_END_UNALIGNED__ = .;
    112         /*
    113          * Memory page(s) mapped to this section will be marked
    114          * as device memory.  No other unexpected data must creep in.
    115          * Ensure the rest of the current memory page is unused.
    116          */
    117         . = NEXT(4096);
    118         __COHERENT_RAM_END__ = .;
    119     } >RAM
    120 #endif
    121 
    122     __BL32_END__ = .;
    123 
    124     __BSS_SIZE__ = SIZEOF(.bss);
    125 #if USE_COHERENT_MEM
    126     __COHERENT_RAM_UNALIGNED_SIZE__ =
    127         __COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
    128 #endif
    129 
    130     ASSERT(. <= BL32_LIMIT, "BL3-2 image has exceeded its limit.")
    131 }
    132