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    Searched defs:__I (Results 1 - 7 of 7) sorted by null

  /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cm0.h 193 #define __I volatile /*!< Defines 'read only' permissions */
195 #define __I volatile const /*!< Defines 'read only' permissions */
336 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
444 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
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core_cm0plus.h 203 #define __I volatile /*!< Defines 'read only' permissions */
205 #define __I volatile const /*!< Defines 'read only' permissions */
347 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
465 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
512 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
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core_sc000.h 198 #define __I volatile /*!< Defines 'read only' permissions */
200 #define __I volatile const /*!< Defines 'read only' permissions */
342 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
484 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
531 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
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core_cm3.h 198 #define __I volatile /*!< Defines 'read only' permissions */
200 #define __I volatile const /*!< Defines 'read only' permissions */
350 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
364 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
365 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
366 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
367 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
368 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
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core_sc300.h 198 #define __I volatile /*!< Defines 'read only' permissions */
200 #define __I volatile const /*!< Defines 'read only' permissions */
350 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
364 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
365 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
366 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
367 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
368 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
    [all...]
core_cm4.h 244 #define __I volatile /*!< Defines 'read only' permissions */
246 #define __I volatile const /*!< Defines 'read only' permissions */
397 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
411 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
412 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
413 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
414 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
415 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
    [all...]
core_cm7.h 259 #define __I volatile /*!< Defines 'read only' permissions */
261 #define __I volatile const /*!< Defines 'read only' permissions */
412 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
426 __I uint32_t ID_PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
427 __I uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
428 __I uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
429 __I uint32_t ID_MFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
430 __I uint32_t ID_ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
432 __I uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */
433 __I uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register (…)
    [all...]

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