| /art/compiler/optimizing/ |
| register_allocation_resolver.cc | 279 size_t core_spills = local
284 core_register_spill_size * core_spills + fp_register_spill_size * fp_spills;
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| code_generator.cc | 1311 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, \/* core_registers *\/ true); local
1335 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, \/* core_registers *\/ true); local
[all...] |
| code_generator_arm64.cc | 171 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); local
173 DCHECK(ArtVixlRegCodeCoherentForRegSet(core_spills,
178 CPURegList core_list = CPURegList(CPURegister::kRegister, kXRegSize, core_spills);
215 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); local
216 for (uint32_t i : LowToHighBits(core_spills)) {
[all...] |
| code_generator_arm.cc | 169 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); local
170 for (uint32_t i : LowToHighBits(core_spills)) {
181 int reg_num = POPCOUNT(core_spills);
184 __ StoreList(RegList(core_spills), orig_offset);
187 for (uint32_t i : LowToHighBits(core_spills)) {
216 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); local
217 for (uint32_t i : LowToHighBits(core_spills)) {
223 int reg_num = POPCOUNT(core_spills);
226 __ LoadList(RegList(core_spills), orig_offset);
229 for (uint32_t i : LowToHighBits(core_spills)) {
[all...] |
| code_generator_arm_vixl.cc | 212 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); local
213 for (uint32_t i : LowToHighBits(core_spills)) {
225 arm_codegen->GetAssembler()->StoreRegisterList(core_spills, orig_offset);
250 const uint32_t core_spills = codegen->GetSlowPathSpills(locations, /* core_registers */ true); local
251 for (uint32_t i : LowToHighBits(core_spills)) {
259 arm_codegen->GetAssembler()->LoadRegisterList(core_spills, orig_offset);
[all...] |
