1 //===-- llvm/Target/TargetMachine.h - Target Information --------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the TargetMachine and LLVMTargetMachine classes. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_TARGET_TARGETMACHINE_H 15 #define LLVM_TARGET_TARGETMACHINE_H 16 17 #include "llvm/ADT/StringRef.h" 18 #include "llvm/ADT/Triple.h" 19 #include "llvm/IR/DataLayout.h" 20 #include "llvm/Pass.h" 21 #include "llvm/Support/CodeGen.h" 22 #include "llvm/Target/TargetOptions.h" 23 #include <cassert> 24 #include <string> 25 26 namespace llvm { 27 28 class InstrItineraryData; 29 class GlobalValue; 30 class Mangler; 31 class MachineFunctionInitializer; 32 class MachineModuleInfo; 33 class MCAsmInfo; 34 class MCContext; 35 class MCInstrInfo; 36 class MCRegisterInfo; 37 class MCSubtargetInfo; 38 class MCSymbol; 39 class Target; 40 class TargetLibraryInfo; 41 class TargetFrameLowering; 42 class TargetIRAnalysis; 43 class TargetIntrinsicInfo; 44 class TargetLowering; 45 class TargetPassConfig; 46 class TargetRegisterInfo; 47 class TargetSubtargetInfo; 48 class TargetTransformInfo; 49 class formatted_raw_ostream; 50 class raw_ostream; 51 class raw_pwrite_stream; 52 class TargetLoweringObjectFile; 53 54 // The old pass manager infrastructure is hidden in a legacy namespace now. 55 namespace legacy { 56 class PassManagerBase; 57 } 58 using legacy::PassManagerBase; 59 60 //===----------------------------------------------------------------------===// 61 /// 62 /// Primary interface to the complete machine description for the target 63 /// machine. All target-specific information should be accessible through this 64 /// interface. 65 /// 66 class TargetMachine { 67 TargetMachine(const TargetMachine &) = delete; 68 void operator=(const TargetMachine &) = delete; 69 protected: // Can only create subclasses. 70 TargetMachine(const Target &T, StringRef DataLayoutString, 71 const Triple &TargetTriple, StringRef CPU, StringRef FS, 72 const TargetOptions &Options); 73 74 /// The Target that this machine was created for. 75 const Target &TheTarget; 76 77 /// DataLayout for the target: keep ABI type size and alignment. 78 /// 79 /// The DataLayout is created based on the string representation provided 80 /// during construction. It is kept here only to avoid reparsing the string 81 /// but should not really be used during compilation, because it has an 82 /// internal cache that is context specific. 83 const DataLayout DL; 84 85 /// Triple string, CPU name, and target feature strings the TargetMachine 86 /// instance is created with. 87 Triple TargetTriple; 88 std::string TargetCPU; 89 std::string TargetFS; 90 91 Reloc::Model RM = Reloc::Static; 92 CodeModel::Model CMModel = CodeModel::Default; 93 CodeGenOpt::Level OptLevel = CodeGenOpt::Default; 94 95 /// Contains target specific asm information. 96 const MCAsmInfo *AsmInfo; 97 98 const MCRegisterInfo *MRI; 99 const MCInstrInfo *MII; 100 const MCSubtargetInfo *STI; 101 102 unsigned RequireStructuredCFG : 1; 103 unsigned O0WantsFastISel : 1; 104 105 public: 106 mutable TargetOptions Options; 107 108 virtual ~TargetMachine(); 109 110 const Target &getTarget() const { return TheTarget; } 111 112 const Triple &getTargetTriple() const { return TargetTriple; } 113 StringRef getTargetCPU() const { return TargetCPU; } 114 StringRef getTargetFeatureString() const { return TargetFS; } 115 116 /// Virtual method implemented by subclasses that returns a reference to that 117 /// target's TargetSubtargetInfo-derived member variable. 118 virtual const TargetSubtargetInfo *getSubtargetImpl(const Function &) const { 119 return nullptr; 120 } 121 virtual TargetLoweringObjectFile *getObjFileLowering() const { 122 return nullptr; 123 } 124 125 /// This method returns a pointer to the specified type of 126 /// TargetSubtargetInfo. In debug builds, it verifies that the object being 127 /// returned is of the correct type. 128 template <typename STC> const STC &getSubtarget(const Function &F) const { 129 return *static_cast<const STC*>(getSubtargetImpl(F)); 130 } 131 132 /// Create a DataLayout. 133 const DataLayout createDataLayout() const { return DL; } 134 135 /// Test if a DataLayout if compatible with the CodeGen for this target. 136 /// 137 /// The LLVM Module owns a DataLayout that is used for the target independent 138 /// optimizations and code generation. This hook provides a target specific 139 /// check on the validity of this DataLayout. 140 bool isCompatibleDataLayout(const DataLayout &Candidate) const { 141 return DL == Candidate; 142 } 143 144 /// Get the pointer size for this target. 145 /// 146 /// This is the only time the DataLayout in the TargetMachine is used. 147 unsigned getPointerSize() const { return DL.getPointerSize(); } 148 149 /// \brief Reset the target options based on the function's attributes. 150 // FIXME: Remove TargetOptions that affect per-function code generation 151 // from TargetMachine. 152 void resetTargetOptions(const Function &F) const; 153 154 /// Return target specific asm information. 155 const MCAsmInfo *getMCAsmInfo() const { return AsmInfo; } 156 157 const MCRegisterInfo *getMCRegisterInfo() const { return MRI; } 158 const MCInstrInfo *getMCInstrInfo() const { return MII; } 159 const MCSubtargetInfo *getMCSubtargetInfo() const { return STI; } 160 161 /// If intrinsic information is available, return it. If not, return null. 162 virtual const TargetIntrinsicInfo *getIntrinsicInfo() const { 163 return nullptr; 164 } 165 166 bool requiresStructuredCFG() const { return RequireStructuredCFG; } 167 void setRequiresStructuredCFG(bool Value) { RequireStructuredCFG = Value; } 168 169 /// Returns the code generation relocation model. The choices are static, PIC, 170 /// and dynamic-no-pic, and target default. 171 Reloc::Model getRelocationModel() const; 172 173 /// Returns the code model. The choices are small, kernel, medium, large, and 174 /// target default. 175 CodeModel::Model getCodeModel() const; 176 177 bool isPositionIndependent() const; 178 179 bool shouldAssumeDSOLocal(const Module &M, const GlobalValue *GV) const; 180 181 /// Returns the TLS model which should be used for the given global variable. 182 TLSModel::Model getTLSModel(const GlobalValue *GV) const; 183 184 /// Returns the optimization level: None, Less, Default, or Aggressive. 185 CodeGenOpt::Level getOptLevel() const; 186 187 /// \brief Overrides the optimization level. 188 void setOptLevel(CodeGenOpt::Level Level); 189 190 void setFastISel(bool Enable) { Options.EnableFastISel = Enable; } 191 bool getO0WantsFastISel() { return O0WantsFastISel; } 192 void setO0WantsFastISel(bool Enable) { O0WantsFastISel = Enable; } 193 194 bool shouldPrintMachineCode() const { return Options.PrintMachineCode; } 195 196 /// Returns the default value of asm verbosity. 197 /// 198 bool getAsmVerbosityDefault() const { 199 return Options.MCOptions.AsmVerbose; 200 } 201 202 bool getUniqueSectionNames() const { return Options.UniqueSectionNames; } 203 204 /// Return true if data objects should be emitted into their own section, 205 /// corresponds to -fdata-sections. 206 bool getDataSections() const { 207 return Options.DataSections; 208 } 209 210 /// Return true if functions should be emitted into their own section, 211 /// corresponding to -ffunction-sections. 212 bool getFunctionSections() const { 213 return Options.FunctionSections; 214 } 215 216 /// \brief Get a \c TargetIRAnalysis appropriate for the target. 217 /// 218 /// This is used to construct the new pass manager's target IR analysis pass, 219 /// set up appropriately for this target machine. Even the old pass manager 220 /// uses this to answer queries about the IR. 221 virtual TargetIRAnalysis getTargetIRAnalysis(); 222 223 /// Add target-specific function passes that should be run as early as 224 /// possible in the optimization pipeline. Most TargetMachines have no such 225 /// passes. 226 virtual void addEarlyAsPossiblePasses(PassManagerBase &) {} 227 228 /// These enums are meant to be passed into addPassesToEmitFile to indicate 229 /// what type of file to emit, and returned by it to indicate what type of 230 /// file could actually be made. 231 enum CodeGenFileType { 232 CGFT_AssemblyFile, 233 CGFT_ObjectFile, 234 CGFT_Null // Do not emit any output. 235 }; 236 237 /// Add passes to the specified pass manager to get the specified file 238 /// emitted. Typically this will involve several steps of code generation. 239 /// This method should return true if emission of this file type is not 240 /// supported, or false on success. 241 virtual bool addPassesToEmitFile( 242 PassManagerBase &, raw_pwrite_stream &, CodeGenFileType, 243 bool /*DisableVerify*/ = true, AnalysisID /*StartBefore*/ = nullptr, 244 AnalysisID /*StartAfter*/ = nullptr, AnalysisID /*StopAfter*/ = nullptr, 245 MachineFunctionInitializer * /*MFInitializer*/ = nullptr) { 246 return true; 247 } 248 249 /// Add passes to the specified pass manager to get machine code emitted with 250 /// the MCJIT. This method returns true if machine code is not supported. It 251 /// fills the MCContext Ctx pointer which can be used to build custom 252 /// MCStreamer. 253 /// 254 virtual bool addPassesToEmitMC(PassManagerBase &, MCContext *&, 255 raw_pwrite_stream &, 256 bool /*DisableVerify*/ = true) { 257 return true; 258 } 259 260 /// True if subtarget inserts the final scheduling pass on its own. 261 /// 262 /// Branch relaxation, which must happen after block placement, can 263 /// on some targets (e.g. SystemZ) expose additional post-RA 264 /// scheduling opportunities. 265 virtual bool targetSchedulesPostRAScheduling() const { return false; }; 266 267 void getNameWithPrefix(SmallVectorImpl<char> &Name, const GlobalValue *GV, 268 Mangler &Mang, bool MayAlwaysUsePrivate = false) const; 269 MCSymbol *getSymbol(const GlobalValue *GV, Mangler &Mang) const; 270 271 /// True if the target uses physical regs at Prolog/Epilog insertion 272 /// time. If true (most machines), all vregs must be allocated before 273 /// PEI. If false (virtual-register machines), then callee-save register 274 /// spilling and scavenging are not needed or used. 275 virtual bool usesPhysRegsForPEI() const { return true; } 276 }; 277 278 /// This class describes a target machine that is implemented with the LLVM 279 /// target-independent code generator. 280 /// 281 class LLVMTargetMachine : public TargetMachine { 282 protected: // Can only create subclasses. 283 LLVMTargetMachine(const Target &T, StringRef DataLayoutString, 284 const Triple &TargetTriple, StringRef CPU, StringRef FS, 285 TargetOptions Options, Reloc::Model RM, CodeModel::Model CM, 286 CodeGenOpt::Level OL); 287 288 void initAsmInfo(); 289 public: 290 /// \brief Get a TargetIRAnalysis implementation for the target. 291 /// 292 /// This analysis will produce a TTI result which uses the common code 293 /// generator to answer queries about the IR. 294 TargetIRAnalysis getTargetIRAnalysis() override; 295 296 /// Create a pass configuration object to be used by addPassToEmitX methods 297 /// for generating a pipeline of CodeGen passes. 298 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM); 299 300 /// Add passes to the specified pass manager to get the specified file 301 /// emitted. Typically this will involve several steps of code generation. 302 bool addPassesToEmitFile( 303 PassManagerBase &PM, raw_pwrite_stream &Out, CodeGenFileType FileType, 304 bool DisableVerify = true, AnalysisID StartBefore = nullptr, 305 AnalysisID StartAfter = nullptr, AnalysisID StopAfter = nullptr, 306 MachineFunctionInitializer *MFInitializer = nullptr) override; 307 308 /// Add passes to the specified pass manager to get machine code emitted with 309 /// the MCJIT. This method returns true if machine code is not supported. It 310 /// fills the MCContext Ctx pointer which can be used to build custom 311 /// MCStreamer. 312 bool addPassesToEmitMC(PassManagerBase &PM, MCContext *&Ctx, 313 raw_pwrite_stream &OS, 314 bool DisableVerify = true) override; 315 316 /// Add MachineModuleInfo pass to pass manager. 317 MachineModuleInfo &addMachineModuleInfo(PassManagerBase &PM) const; 318 319 /// Add MachineFunctionAnalysis pass to pass manager. 320 void addMachineFunctionAnalysis(PassManagerBase &PM, 321 MachineFunctionInitializer *MFInitializer) const; 322 }; 323 324 } // End llvm namespace 325 326 #endif 327
