1 //===- TargetRegisterInfo.cpp - Target Register Information Implementation ===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the TargetRegisterInfo interface. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/Target/TargetMachine.h" 15 #include "llvm/Target/TargetRegisterInfo.h" 16 #include "llvm/CodeGen/MachineFunction.h" 17 #include "llvm/CodeGen/MachineFrameInfo.h" 18 #include "llvm/ADT/BitVector.h" 19 #include "llvm/Support/raw_ostream.h" 20 21 using namespace llvm; 22 23 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID, 24 regclass_iterator RCB, regclass_iterator RCE, 25 const char *const *subregindexnames) 26 : InfoDesc(ID), SubRegIndexNames(subregindexnames), 27 RegClassBegin(RCB), RegClassEnd(RCE) { 28 } 29 30 TargetRegisterInfo::~TargetRegisterInfo() {} 31 32 void PrintReg::print(raw_ostream &OS) const { 33 if (!Reg) 34 OS << "%noreg"; 35 else if (TargetRegisterInfo::isStackSlot(Reg)) 36 OS << "SS#" << TargetRegisterInfo::stackSlot2Index(Reg); 37 else if (TargetRegisterInfo::isVirtualRegister(Reg)) 38 OS << "%vreg" << TargetRegisterInfo::virtReg2Index(Reg); 39 else if (TRI && Reg < TRI->getNumRegs()) 40 OS << '%' << TRI->getName(Reg); 41 else 42 OS << "%physreg" << Reg; 43 if (SubIdx) { 44 if (TRI) 45 OS << ':' << TRI->getSubRegIndexName(SubIdx); 46 else 47 OS << ":sub(" << SubIdx << ')'; 48 } 49 } 50 51 /// getMinimalPhysRegClass - Returns the Register Class of a physical 52 /// register of the given type, picking the most sub register class of 53 /// the right type that contains this physreg. 54 const TargetRegisterClass * 55 TargetRegisterInfo::getMinimalPhysRegClass(unsigned reg, EVT VT) const { 56 assert(isPhysicalRegister(reg) && "reg must be a physical register"); 57 58 // Pick the most sub register class of the right type that contains 59 // this physreg. 60 const TargetRegisterClass* BestRC = 0; 61 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){ 62 const TargetRegisterClass* RC = *I; 63 if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) && 64 (!BestRC || BestRC->hasSubClass(RC))) 65 BestRC = RC; 66 } 67 68 assert(BestRC && "Couldn't find the register class"); 69 return BestRC; 70 } 71 72 /// getAllocatableSetForRC - Toggle the bits that represent allocatable 73 /// registers for the specific register class. 74 static void getAllocatableSetForRC(const MachineFunction &MF, 75 const TargetRegisterClass *RC, BitVector &R){ 76 ArrayRef<unsigned> Order = RC->getRawAllocationOrder(MF); 77 for (unsigned i = 0; i != Order.size(); ++i) 78 R.set(Order[i]); 79 } 80 81 BitVector TargetRegisterInfo::getAllocatableSet(const MachineFunction &MF, 82 const TargetRegisterClass *RC) const { 83 BitVector Allocatable(getNumRegs()); 84 if (RC) { 85 getAllocatableSetForRC(MF, RC, Allocatable); 86 } else { 87 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(), 88 E = regclass_end(); I != E; ++I) 89 if ((*I)->isAllocatable()) 90 getAllocatableSetForRC(MF, *I, Allocatable); 91 } 92 93 // Mask out the reserved registers 94 BitVector Reserved = getReservedRegs(MF); 95 Allocatable &= Reserved.flip(); 96 97 return Allocatable; 98 } 99 100 const TargetRegisterClass * 101 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A, 102 const TargetRegisterClass *B) const { 103 // First take care of the trivial cases. 104 if (A == B) 105 return A; 106 if (!A || !B) 107 return 0; 108 109 // Register classes are ordered topologically, so the largest common 110 // sub-class it the common sub-class with the smallest ID. 111 const unsigned *SubA = A->getSubClassMask(); 112 const unsigned *SubB = B->getSubClassMask(); 113 114 // We could start the search from max(A.ID, B.ID), but we are only going to 115 // execute 2-3 iterations anyway. 116 for (unsigned Base = 0, BaseE = getNumRegClasses(); Base < BaseE; Base += 32) 117 if (unsigned Common = *SubA++ & *SubB++) 118 return getRegClass(Base + CountTrailingZeros_32(Common)); 119 120 // No common sub-class exists. 121 return NULL; 122 } 123