/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
AMDGPUMCCodeEmitter.h | 35 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SIMCCodeEmitter.cpp | 59 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 254 return getMachineOpValue(MI, MO, Fixups, STI); 257 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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R600MCCodeEmitter.cpp | 50 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 155 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
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/external/mesa3d/src/gallium/drivers/radeon/ |
AMDGPUCodeEmitter.h | 22 virtual uint64_t getMachineOpValue(const MachineInstr &MI,
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/external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
AMDGPUMCCodeEmitter.h | 31 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SIMCCodeEmitter.cpp | 77 /// getMachineOpValue - Reutrn the encoding for an MCOperand. 78 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 140 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, 207 (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK)
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R600MCCodeEmitter.cpp | 56 /// getMachineOpValue - Reutrn the encoding for an MCOperand. 57 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 620 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI,
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/ |
PPCMCCodeEmitter.cpp | 53 /// getMachineOpValue - Return binary encoding of operand. If the machine 55 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 100 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 122 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); 135 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16; 139 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits; 153 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14; 157 return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits [all...] |
/external/llvm/lib/Target/BPF/MCTargetDesc/ |
BPFMCCodeEmitter.cpp | 48 // getMachineOpValue - Return binary encoding of operand. If the machin 50 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 76 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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/external/llvm/lib/Target/Sparc/MCTargetDesc/ |
SparcMCCodeEmitter.cpp | 55 /// getMachineOpValue - Return binary encoding of operand. If the machine 57 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 106 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI); 116 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 148 return getMachineOpValue(MI, MO, Fixups, STI); 183 return getMachineOpValue(MI, MO, Fixups, STI); 196 return getMachineOpValue(MI, MO, Fixups, STI); 208 return getMachineOpValue(MI, MO, Fixups, STI);
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/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/ |
MBlazeMCCodeEmitter.cpp | 48 /// getMachineOpValue - Return binary encoding of operand. If the machine 50 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const; 51 unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const { 52 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 106 /// getMachineOpValue - Return binary encoding of operand. If the machine 108 unsigned MBlazeMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
PPCCodeEmitter.cpp | 59 /// getMachineOpValue - evaluates the MachineOperand of a given MachineInstr 60 unsigned getMachineOpValue(const MachineInstr &MI, 182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 198 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); 218 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16; 222 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits; 234 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14; 238 return (getMachineOpValue(MI, MO) & 0x3FFF) | RegBits; 245 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI [all...] |
/external/llvm/lib/Target/Lanai/MCTargetDesc/ |
LanaiMCCodeEmitter.cpp | 56 // getMachineOpValue - Return binary encoding of operand. If the machine 58 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp, 110 // getMachineOpValue - Return binary encoding of operand. If the machine 112 unsigned LanaiMCCodeEmitter::getMachineOpValue( 215 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo); 286 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo); 296 return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo); 309 return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo);
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
PPCMCCodeEmitter.cpp | 94 /// getMachineOpValue - Return binary encoding of operand. If the machine 96 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); 221 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; 225 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; 240 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14 [all...] |
/external/llvm/lib/Target/SystemZ/MCTargetDesc/ |
SystemZMCCodeEmitter.cpp | 52 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, 137 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 151 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 152 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 161 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 162 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 171 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); 172 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); 173 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); 182 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI) [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
MipsCodeEmitter.cpp | 100 /// getMachineOpValue - Return binary encoding of operand. If the machine 102 unsigned getMachineOpValue(const MachineInstr &MI, 163 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16; 165 (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits; 171 return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; 177 return getMachineOpValue(MI, MI.getOperand(OpNo-1)) + 178 getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; 181 /// getMachineOpValue - Return binary encoding of operand. If the machine 183 unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI,
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/external/llvm/lib/Target/AArch64/MCTargetDesc/ |
AArch64MCCodeEmitter.cpp | 52 /// getMachineOpValue - Return binary encoding of operand. If the machine 54 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO, 183 /// getMachineOpValue - Return binary encoding of operand. If the machine 186 AArch64MCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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/external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
HexagonMCCodeEmitter.cpp | 792 HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO,
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/external/llvm/lib/Target/Mips/MCTargetDesc/ |
MipsMCCodeEmitter.cpp | 560 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); 757 /// getMachineOpValue - Return binary encoding of operand. If the machine 760 getMachineOpValue(const MCInst &MI, const MCOperand &MO, 786 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; 787 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); 801 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), 803 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), 815 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), 817 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), 829 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo) [all...] |
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | 72 /// getMachineOpValue - Return binary encoding of operand. If the machine 74 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 519 /// getMachineOpValue - Return binary encoding of operand. If the machine 522 getMachineOpValue(const MCInst &MI, const MCOperand &MO, [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
ARMCodeEmitter.cpp | 148 /// getMachineOpValue - Return binary encoding of operand. If the machine 150 unsigned getMachineOpValue(const MachineInstr &MI, 152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { 153 return getMachineOpValue(MI, MI.getOperand(OpIdx)); 158 // operand values, instead querying getMachineOpValue() directly for 437 /// getMachineOpValue - Return binary encoding of operand. If the machine 439 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, 697 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 712 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; 735 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
ARMMCCodeEmitter.cpp | 70 /// getMachineOpValue - Return binary encoding of operand. If the machine 72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO, 399 /// getMachineOpValue - Return binary encoding of operand. If the machine 402 getMachineOpValue(const MCInst &MI, const MCOperand &MO, [all...] |