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      1 /*
      2  * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
      3  *
      4  * Redistribution and use in source and binary forms, with or without
      5  * modification, are permitted provided that the following conditions are met:
      6  *
      7  * Redistributions of source code must retain the above copyright notice, this
      8  * list of conditions and the following disclaimer.
      9  *
     10  * Redistributions in binary form must reproduce the above copyright notice,
     11  * this list of conditions and the following disclaimer in the documentation
     12  * and/or other materials provided with the distribution.
     13  *
     14  * Neither the name of ARM nor the names of its contributors may be used
     15  * to endorse or promote products derived from this software without specific
     16  * prior written permission.
     17  *
     18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
     19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     21  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
     22  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     28  * POSSIBILITY OF SUCH DAMAGE.
     29  */
     30 
     31 #ifndef __GIC_V3_H__
     32 #define __GIC_V3_H__
     33 
     34 #include <mmio.h>
     35 #include <stdint.h>
     36 
     37 
     38 /* GICv3 Re-distributor interface registers & shifts */
     39 #define GICR_PCPUBASE_SHIFT	0x11
     40 #define GICR_TYPER		0x08
     41 #define GICR_WAKER		0x14
     42 
     43 /* GICR_WAKER bit definitions */
     44 #define WAKER_CA		(1UL << 2)
     45 #define WAKER_PS		(1UL << 1)
     46 
     47 /* GICR_TYPER bit definitions */
     48 #define GICR_TYPER_AFF_SHIFT	32
     49 #define GICR_TYPER_AFF_MASK	0xffffffff
     50 #define GICR_TYPER_LAST		(1UL << 4)
     51 
     52 /* GICv3 ICC_SRE register bit definitions*/
     53 #define ICC_SRE_EN		(1UL << 3)
     54 #define ICC_SRE_SRE		(1UL << 0)
     55 
     56 /*******************************************************************************
     57  * GICv3 defintions
     58  ******************************************************************************/
     59 #define GICV3_AFFLVL_MASK	0xff
     60 #define GICV3_AFF0_SHIFT	0
     61 #define GICV3_AFF1_SHIFT	8
     62 #define GICV3_AFF2_SHIFT	16
     63 #define GICV3_AFF3_SHIFT	24
     64 #define GICV3_AFFINITY_MASK	0xffffffff
     65 
     66 /*******************************************************************************
     67  * Function prototypes
     68  ******************************************************************************/
     69 uintptr_t gicv3_get_rdist(uintptr_t gicr_base, uint64_t mpidr);
     70 
     71 /*******************************************************************************
     72  * GIC Redistributor interface accessors
     73  ******************************************************************************/
     74 static inline uint32_t gicr_read_waker(uintptr_t base)
     75 {
     76 	return mmio_read_32(base + GICR_WAKER);
     77 }
     78 
     79 static inline void gicr_write_waker(uintptr_t base, uint32_t val)
     80 {
     81 	mmio_write_32(base + GICR_WAKER, val);
     82 }
     83 
     84 static inline uint64_t gicr_read_typer(uintptr_t base)
     85 {
     86 	return mmio_read_64(base + GICR_TYPER);
     87 }
     88 
     89 
     90 #endif /* __GIC_V3_H__ */
     91