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      1 //=====-- MipsSubtarget.h - Define Subtarget for the Mips -----*- C++ -*--====//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #ifndef MIPSSUBTARGET_H
     15 #define MIPSSUBTARGET_H
     16 
     17 #include "llvm/Target/TargetSubtargetInfo.h"
     18 #include "llvm/MC/MCInstrItineraries.h"
     19 #include <string>
     20 
     21 #define GET_SUBTARGETINFO_HEADER
     22 #include "MipsGenSubtargetInfo.inc"
     23 
     24 namespace llvm {
     25 class StringRef;
     26 
     27 class MipsSubtarget : public MipsGenSubtargetInfo {
     28 
     29 public:
     30   // NOTE: O64 will not be supported.
     31   enum MipsABIEnum {
     32     UnknownABI, O32, N32, N64, EABI
     33   };
     34 
     35 protected:
     36 
     37   enum MipsArchEnum {
     38     Mips32, Mips32r2, Mips64, Mips64r2
     39   };
     40 
     41   // Mips architecture version
     42   MipsArchEnum MipsArchVersion;
     43 
     44   // Mips supported ABIs
     45   MipsABIEnum MipsABI;
     46 
     47   // IsLittle - The target is Little Endian
     48   bool IsLittle;
     49 
     50   // IsSingleFloat - The target only supports single precision float
     51   // point operations. This enable the target to use all 32 32-bit
     52   // floating point registers instead of only using even ones.
     53   bool IsSingleFloat;
     54 
     55   // IsFP64bit - The target processor has 64-bit floating point registers.
     56   bool IsFP64bit;
     57 
     58   // IsFP64bit - General-purpose registers are 64 bits wide
     59   bool IsGP64bit;
     60 
     61   // HasVFPU - Processor has a vector floating point unit.
     62   bool HasVFPU;
     63 
     64   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
     65   bool IsLinux;
     66 
     67   /// Features related to the presence of specific instructions.
     68 
     69   // HasSEInReg - SEB and SEH (signext in register) instructions.
     70   bool HasSEInReg;
     71 
     72   // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
     73   bool HasCondMov;
     74 
     75   // HasMulDivAdd - Multiply add and sub (MADD, MADDu, MSUB, MSUBu)
     76   // instructions.
     77   bool HasMulDivAdd;
     78 
     79   // HasMinMax - MIN and MAX instructions.
     80   bool HasMinMax;
     81 
     82   // HasSwap - Byte and half swap instructions.
     83   bool HasSwap;
     84 
     85   // HasBitCount - Count leading '1' and '0' bits.
     86   bool HasBitCount;
     87 
     88   InstrItineraryData InstrItins;
     89 
     90 public:
     91 
     92   /// Only O32 and EABI supported right now.
     93   bool isABI_EABI() const { return MipsABI == EABI; }
     94   bool isABI_N64() const { return MipsABI == N64; }
     95   bool isABI_N32() const { return MipsABI == N32; }
     96   bool isABI_O32() const { return MipsABI == O32; }
     97   unsigned getTargetABI() const { return MipsABI; }
     98 
     99   /// This constructor initializes the data members to match that
    100   /// of the specified triple.
    101   MipsSubtarget(const std::string &TT, const std::string &CPU,
    102                 const std::string &FS, bool little);
    103 
    104   /// ParseSubtargetFeatures - Parses features string setting specified
    105   /// subtarget options.  Definition of function is auto generated by tblgen.
    106   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
    107 
    108   bool hasMips32() const { return MipsArchVersion >= Mips32; }
    109   bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
    110                                    MipsArchVersion == Mips64r2; }
    111   bool hasMips64() const { return MipsArchVersion >= Mips64; }
    112   bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
    113 
    114   bool isLittle() const { return IsLittle; }
    115   bool isFP64bit() const { return IsFP64bit; }
    116   bool isGP64bit() const { return IsGP64bit; }
    117   bool isGP32bit() const { return !IsGP64bit; }
    118   bool isSingleFloat() const { return IsSingleFloat; }
    119   bool isNotSingleFloat() const { return !IsSingleFloat; }
    120   bool hasVFPU() const { return HasVFPU; }
    121   bool isLinux() const { return IsLinux; }
    122 
    123   /// Features related to the presence of specific instructions.
    124   bool hasSEInReg()   const { return HasSEInReg; }
    125   bool hasCondMov()   const { return HasCondMov; }
    126   bool hasMulDivAdd() const { return HasMulDivAdd; }
    127   bool hasMinMax()    const { return HasMinMax; }
    128   bool hasSwap()      const { return HasSwap; }
    129   bool hasBitCount()  const { return HasBitCount; }
    130 };
    131 } // End llvm namespace
    132 
    133 #endif
    134