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      1 /*
      2  * Copyright (C) 2011 The Android Open Source Project
      3  *
      4  * Licensed under the Apache License, Version 2.0 (the "License");
      5  * you may not use this file except in compliance with the License.
      6  * You may obtain a copy of the License at
      7  *
      8  *      http://www.apache.org/licenses/LICENSE-2.0
      9  *
     10  * Unless required by applicable law or agreed to in writing, software
     11  * distributed under the License is distributed on an "AS IS" BASIS,
     12  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
     13  * See the License for the specific language governing permissions and
     14  * limitations under the License.
     15  */
     16 
     17 #ifndef ART_RUNTIME_DEX_INSTRUCTION_H_
     18 #define ART_RUNTIME_DEX_INSTRUCTION_H_
     19 
     20 #include "base/logging.h"
     21 #include "base/macros.h"
     22 #include "globals.h"
     23 
     24 typedef uint8_t uint4_t;
     25 typedef int8_t int4_t;
     26 
     27 namespace art {
     28 
     29 class DexFile;
     30 
     31 enum {
     32   kNumPackedOpcodes = 0x100
     33 };
     34 
     35 class Instruction {
     36  public:
     37   // NOP-encoded switch-statement signatures.
     38   enum Signatures {
     39     kPackedSwitchSignature = 0x0100,
     40     kSparseSwitchSignature = 0x0200,
     41     kArrayDataSignature = 0x0300,
     42   };
     43 
     44   struct PACKED(4) PackedSwitchPayload {
     45     const uint16_t ident;
     46     const uint16_t case_count;
     47     const int32_t first_key;
     48     const int32_t targets[];
     49 
     50    private:
     51     DISALLOW_COPY_AND_ASSIGN(PackedSwitchPayload);
     52   };
     53 
     54   struct PACKED(4) SparseSwitchPayload {
     55     const uint16_t ident;
     56     const uint16_t case_count;
     57     const int32_t keys_and_targets[];
     58 
     59    public:
     60     const int32_t* GetKeys() const {
     61       return keys_and_targets;
     62     }
     63 
     64     const int32_t* GetTargets() const {
     65       return keys_and_targets + case_count;
     66     }
     67 
     68    private:
     69     DISALLOW_COPY_AND_ASSIGN(SparseSwitchPayload);
     70   };
     71 
     72   struct PACKED(4) ArrayDataPayload {
     73     const uint16_t ident;
     74     const uint16_t element_width;
     75     const uint32_t element_count;
     76     const uint8_t data[];
     77 
     78    private:
     79     DISALLOW_COPY_AND_ASSIGN(ArrayDataPayload);
     80   };
     81 
     82   enum Code {  // private marker to avoid generate-operator-out.py from processing.
     83 #define INSTRUCTION_ENUM(opcode, cname, p, f, i, a, v) cname = (opcode),
     84 #include "dex_instruction_list.h"
     85     DEX_INSTRUCTION_LIST(INSTRUCTION_ENUM)
     86 #undef DEX_INSTRUCTION_LIST
     87 #undef INSTRUCTION_ENUM
     88     RSUB_INT_LIT16 = RSUB_INT,
     89   };
     90 
     91   enum Format {
     92     k10x,  // op
     93     k12x,  // op vA, vB
     94     k11n,  // op vA, #+B
     95     k11x,  // op vAA
     96     k10t,  // op +AA
     97     k20t,  // op +AAAA
     98     k22x,  // op vAA, vBBBB
     99     k21t,  // op vAA, +BBBB
    100     k21s,  // op vAA, #+BBBB
    101     k21h,  // op vAA, #+BBBB00000[00000000]
    102     k21c,  // op vAA, thing@BBBB
    103     k23x,  // op vAA, vBB, vCC
    104     k22b,  // op vAA, vBB, #+CC
    105     k22t,  // op vA, vB, +CCCC
    106     k22s,  // op vA, vB, #+CCCC
    107     k22c,  // op vA, vB, thing@CCCC
    108     k32x,  // op vAAAA, vBBBB
    109     k30t,  // op +AAAAAAAA
    110     k31t,  // op vAA, +BBBBBBBB
    111     k31i,  // op vAA, #+BBBBBBBB
    112     k31c,  // op vAA, thing@BBBBBBBB
    113     k35c,  // op {vC, vD, vE, vF, vG}, thing@BBBB (B: count, A: vG)
    114     k3rc,  // op {vCCCC .. v(CCCC+AA-1)}, meth@BBBB
    115 
    116     // op {vC, vD, vE, vF, vG}, meth@BBBB, proto@HHHH (A: count)
    117     // format: AG op BBBB FEDC HHHH
    118     k45cc,
    119 
    120     // op {VCCCC .. v(CCCC+AA-1)}, meth@BBBB, proto@HHHH (AA: count)
    121     // format: AA op BBBB CCCC HHHH
    122     k4rcc,  // op {VCCCC .. v(CCCC+AA-1)}, meth@BBBB, proto@HHHH (AA: count)
    123 
    124     k51l,  // op vAA, #+BBBBBBBBBBBBBBBB
    125   };
    126 
    127   enum IndexType {
    128     kIndexUnknown = 0,
    129     kIndexNone,               // has no index
    130     kIndexTypeRef,            // type reference index
    131     kIndexStringRef,          // string reference index
    132     kIndexMethodRef,          // method reference index
    133     kIndexFieldRef,           // field reference index
    134     kIndexFieldOffset,        // field offset (for static linked fields)
    135     kIndexVtableOffset,       // vtable offset (for static linked methods)
    136     kIndexMethodAndProtoRef,  // method and a proto reference index (for invoke-polymorphic)
    137     kIndexCallSiteRef,        // call site reference index
    138   };
    139 
    140   enum Flags {
    141     kBranch              = 0x0000001,  // conditional or unconditional branch
    142     kContinue            = 0x0000002,  // flow can continue to next statement
    143     kSwitch              = 0x0000004,  // switch statement
    144     kThrow               = 0x0000008,  // could cause an exception to be thrown
    145     kReturn              = 0x0000010,  // returns, no additional statements
    146     kInvoke              = 0x0000020,  // a flavor of invoke
    147     kUnconditional       = 0x0000040,  // unconditional branch
    148     kAdd                 = 0x0000080,  // addition
    149     kSubtract            = 0x0000100,  // subtract
    150     kMultiply            = 0x0000200,  // multiply
    151     kDivide              = 0x0000400,  // division
    152     kRemainder           = 0x0000800,  // remainder
    153     kAnd                 = 0x0001000,  // and
    154     kOr                  = 0x0002000,  // or
    155     kXor                 = 0x0004000,  // xor
    156     kShl                 = 0x0008000,  // shl
    157     kShr                 = 0x0010000,  // shr
    158     kUshr                = 0x0020000,  // ushr
    159     kCast                = 0x0040000,  // cast
    160     kStore               = 0x0080000,  // store opcode
    161     kLoad                = 0x0100000,  // load opcode
    162     kClobber             = 0x0200000,  // clobbers memory in a big way (not just a write)
    163     kRegCFieldOrConstant = 0x0400000,  // is the third virtual register a field or literal constant (vC)
    164     kRegBFieldOrConstant = 0x0800000,  // is the second virtual register a field or literal constant (vB)
    165     kExperimental        = 0x1000000,  // is an experimental opcode
    166   };
    167 
    168   enum VerifyFlag {
    169     kVerifyNone               = 0x0000000,
    170     kVerifyRegA               = 0x0000001,
    171     kVerifyRegAWide           = 0x0000002,
    172     kVerifyRegB               = 0x0000004,
    173     kVerifyRegBField          = 0x0000008,
    174     kVerifyRegBMethod         = 0x0000010,
    175     kVerifyRegBNewInstance    = 0x0000020,
    176     kVerifyRegBString         = 0x0000040,
    177     kVerifyRegBType           = 0x0000080,
    178     kVerifyRegBWide           = 0x0000100,
    179     kVerifyRegC               = 0x0000200,
    180     kVerifyRegCField          = 0x0000400,
    181     kVerifyRegCNewArray       = 0x0000800,
    182     kVerifyRegCType           = 0x0001000,
    183     kVerifyRegCWide           = 0x0002000,
    184     kVerifyArrayData          = 0x0004000,
    185     kVerifyBranchTarget       = 0x0008000,
    186     kVerifySwitchTargets      = 0x0010000,
    187     kVerifyVarArg             = 0x0020000,
    188     kVerifyVarArgNonZero      = 0x0040000,
    189     kVerifyVarArgRange        = 0x0080000,
    190     kVerifyVarArgRangeNonZero = 0x0100000,
    191     kVerifyRuntimeOnly        = 0x0200000,
    192     kVerifyError              = 0x0400000,
    193     kVerifyRegHPrototype      = 0x0800000,
    194     kVerifyRegBCallSite       = 0x1000000
    195   };
    196 
    197   static constexpr uint32_t kMaxVarArgRegs = 5;
    198 
    199   // Returns the size (in 2 byte code units) of this instruction.
    200   size_t SizeInCodeUnits() const {
    201     int result = kInstructionSizeInCodeUnits[Opcode()];
    202     if (UNLIKELY(result < 0)) {
    203       return SizeInCodeUnitsComplexOpcode();
    204     } else {
    205       return static_cast<size_t>(result);
    206     }
    207   }
    208 
    209   // Reads an instruction out of the stream at the specified address.
    210   static const Instruction* At(const uint16_t* code) {
    211     DCHECK(code != nullptr);
    212     return reinterpret_cast<const Instruction*>(code);
    213   }
    214 
    215   // Reads an instruction out of the stream from the current address plus an offset.
    216   const Instruction* RelativeAt(int32_t offset) const WARN_UNUSED {
    217     return At(reinterpret_cast<const uint16_t*>(this) + offset);
    218   }
    219 
    220   // Returns a pointer to the next instruction in the stream.
    221   const Instruction* Next() const {
    222     return RelativeAt(SizeInCodeUnits());
    223   }
    224 
    225   // Returns a pointer to the instruction after this 1xx instruction in the stream.
    226   const Instruction* Next_1xx() const {
    227     DCHECK(FormatOf(Opcode()) >= k10x && FormatOf(Opcode()) <= k10t);
    228     return RelativeAt(1);
    229   }
    230 
    231   // Returns a pointer to the instruction after this 2xx instruction in the stream.
    232   const Instruction* Next_2xx() const {
    233     DCHECK(FormatOf(Opcode()) >= k20t && FormatOf(Opcode()) <= k22c);
    234     return RelativeAt(2);
    235   }
    236 
    237   // Returns a pointer to the instruction after this 3xx instruction in the stream.
    238   const Instruction* Next_3xx() const {
    239     DCHECK(FormatOf(Opcode()) >= k32x && FormatOf(Opcode()) <= k3rc);
    240     return RelativeAt(3);
    241   }
    242 
    243   // Returns a pointer to the instruction after this 4xx instruction in the stream.
    244   const Instruction* Next_4xx() const {
    245     DCHECK(FormatOf(Opcode()) >= k45cc && FormatOf(Opcode()) <= k4rcc);
    246     return RelativeAt(4);
    247   }
    248 
    249   // Returns a pointer to the instruction after this 51l instruction in the stream.
    250   const Instruction* Next_51l() const {
    251     DCHECK(FormatOf(Opcode()) == k51l);
    252     return RelativeAt(5);
    253   }
    254 
    255   // Returns the name of this instruction's opcode.
    256   const char* Name() const {
    257     return Instruction::Name(Opcode());
    258   }
    259 
    260   // Returns the name of the given opcode.
    261   static const char* Name(Code opcode) {
    262     return kInstructionNames[opcode];
    263   }
    264 
    265   // VRegA
    266   bool HasVRegA() const;
    267   ALWAYS_INLINE int32_t VRegA() const;
    268 
    269   int8_t VRegA_10t() const {
    270     return VRegA_10t(Fetch16(0));
    271   }
    272   uint8_t VRegA_10x() const {
    273     return VRegA_10x(Fetch16(0));
    274   }
    275   uint4_t VRegA_11n() const {
    276     return VRegA_11n(Fetch16(0));
    277   }
    278   uint8_t VRegA_11x() const {
    279     return VRegA_11x(Fetch16(0));
    280   }
    281   uint4_t VRegA_12x() const {
    282     return VRegA_12x(Fetch16(0));
    283   }
    284   int16_t VRegA_20t() const;
    285   uint8_t VRegA_21c() const {
    286     return VRegA_21c(Fetch16(0));
    287   }
    288   uint8_t VRegA_21h() const {
    289     return VRegA_21h(Fetch16(0));
    290   }
    291   uint8_t VRegA_21s() const {
    292     return VRegA_21s(Fetch16(0));
    293   }
    294   uint8_t VRegA_21t() const {
    295     return VRegA_21t(Fetch16(0));
    296   }
    297   uint8_t VRegA_22b() const {
    298     return VRegA_22b(Fetch16(0));
    299   }
    300   uint4_t VRegA_22c() const {
    301     return VRegA_22c(Fetch16(0));
    302   }
    303   uint4_t VRegA_22s() const {
    304     return VRegA_22s(Fetch16(0));
    305   }
    306   uint4_t VRegA_22t() const {
    307     return VRegA_22t(Fetch16(0));
    308   }
    309   uint8_t VRegA_22x() const {
    310     return VRegA_22x(Fetch16(0));
    311   }
    312   uint8_t VRegA_23x() const {
    313     return VRegA_23x(Fetch16(0));
    314   }
    315   int32_t VRegA_30t() const;
    316   uint8_t VRegA_31c() const {
    317     return VRegA_31c(Fetch16(0));
    318   }
    319   uint8_t VRegA_31i() const {
    320     return VRegA_31i(Fetch16(0));
    321   }
    322   uint8_t VRegA_31t() const {
    323     return VRegA_31t(Fetch16(0));
    324   }
    325   uint16_t VRegA_32x() const;
    326   uint4_t VRegA_35c() const {
    327     return VRegA_35c(Fetch16(0));
    328   }
    329   uint8_t VRegA_3rc() const {
    330     return VRegA_3rc(Fetch16(0));
    331   }
    332   uint8_t VRegA_51l() const {
    333     return VRegA_51l(Fetch16(0));
    334   }
    335   uint4_t VRegA_45cc() const {
    336     return VRegA_45cc(Fetch16(0));
    337   }
    338   uint8_t VRegA_4rcc() const {
    339     return VRegA_4rcc(Fetch16(0));
    340   }
    341 
    342   // The following methods return the vA operand for various instruction formats. The "inst_data"
    343   // parameter holds the first 16 bits of instruction which the returned value is decoded from.
    344   int8_t VRegA_10t(uint16_t inst_data) const;
    345   uint8_t VRegA_10x(uint16_t inst_data) const;
    346   uint4_t VRegA_11n(uint16_t inst_data) const;
    347   uint8_t VRegA_11x(uint16_t inst_data) const;
    348   uint4_t VRegA_12x(uint16_t inst_data) const;
    349   uint8_t VRegA_21c(uint16_t inst_data) const;
    350   uint8_t VRegA_21h(uint16_t inst_data) const;
    351   uint8_t VRegA_21s(uint16_t inst_data) const;
    352   uint8_t VRegA_21t(uint16_t inst_data) const;
    353   uint8_t VRegA_22b(uint16_t inst_data) const;
    354   uint4_t VRegA_22c(uint16_t inst_data) const;
    355   uint4_t VRegA_22s(uint16_t inst_data) const;
    356   uint4_t VRegA_22t(uint16_t inst_data) const;
    357   uint8_t VRegA_22x(uint16_t inst_data) const;
    358   uint8_t VRegA_23x(uint16_t inst_data) const;
    359   uint8_t VRegA_31c(uint16_t inst_data) const;
    360   uint8_t VRegA_31i(uint16_t inst_data) const;
    361   uint8_t VRegA_31t(uint16_t inst_data) const;
    362   uint4_t VRegA_35c(uint16_t inst_data) const;
    363   uint8_t VRegA_3rc(uint16_t inst_data) const;
    364   uint8_t VRegA_51l(uint16_t inst_data) const;
    365   uint4_t VRegA_45cc(uint16_t inst_data) const;
    366   uint8_t VRegA_4rcc(uint16_t inst_data) const;
    367 
    368   // VRegB
    369   bool HasVRegB() const;
    370   int32_t VRegB() const;
    371 
    372   bool HasWideVRegB() const;
    373   uint64_t WideVRegB() const;
    374 
    375   int4_t VRegB_11n() const {
    376     return VRegB_11n(Fetch16(0));
    377   }
    378   uint4_t VRegB_12x() const {
    379     return VRegB_12x(Fetch16(0));
    380   }
    381   uint16_t VRegB_21c() const;
    382   uint16_t VRegB_21h() const;
    383   int16_t VRegB_21s() const;
    384   int16_t VRegB_21t() const;
    385   uint8_t VRegB_22b() const;
    386   uint4_t VRegB_22c() const {
    387     return VRegB_22c(Fetch16(0));
    388   }
    389   uint4_t VRegB_22s() const {
    390     return VRegB_22s(Fetch16(0));
    391   }
    392   uint4_t VRegB_22t() const {
    393     return VRegB_22t(Fetch16(0));
    394   }
    395   uint16_t VRegB_22x() const;
    396   uint8_t VRegB_23x() const;
    397   uint32_t VRegB_31c() const;
    398   int32_t VRegB_31i() const;
    399   int32_t VRegB_31t() const;
    400   uint16_t VRegB_32x() const;
    401   uint16_t VRegB_35c() const;
    402   uint16_t VRegB_3rc() const;
    403   uint64_t VRegB_51l() const;  // vB_wide
    404   uint16_t VRegB_45cc() const;
    405   uint16_t VRegB_4rcc() const;
    406 
    407   // The following methods return the vB operand for all instruction formats where it is encoded in
    408   // the first 16 bits of instruction. The "inst_data" parameter holds these 16 bits. The returned
    409   // value is decoded from it.
    410   int4_t VRegB_11n(uint16_t inst_data) const;
    411   uint4_t VRegB_12x(uint16_t inst_data) const;
    412   uint4_t VRegB_22c(uint16_t inst_data) const;
    413   uint4_t VRegB_22s(uint16_t inst_data) const;
    414   uint4_t VRegB_22t(uint16_t inst_data) const;
    415 
    416   // VRegC
    417   bool HasVRegC() const;
    418   int32_t VRegC() const;
    419 
    420   int8_t VRegC_22b() const;
    421   uint16_t VRegC_22c() const;
    422   int16_t VRegC_22s() const;
    423   int16_t VRegC_22t() const;
    424   uint8_t VRegC_23x() const;
    425   uint4_t VRegC_35c() const;
    426   uint16_t VRegC_3rc() const;
    427   uint4_t VRegC_45cc() const;
    428   uint16_t VRegC_4rcc() const;
    429 
    430 
    431   // VRegH
    432   bool HasVRegH() const;
    433   int32_t VRegH() const;
    434   uint16_t VRegH_45cc() const;
    435   uint16_t VRegH_4rcc() const;
    436 
    437   // Fills the given array with the 'arg' array of the instruction.
    438   bool HasVarArgs() const;
    439   void GetVarArgs(uint32_t args[kMaxVarArgRegs], uint16_t inst_data) const;
    440   void GetVarArgs(uint32_t args[kMaxVarArgRegs]) const {
    441     return GetVarArgs(args, Fetch16(0));
    442   }
    443 
    444   // Returns the opcode field of the instruction. The given "inst_data" parameter must be the first
    445   // 16 bits of instruction.
    446   Code Opcode(uint16_t inst_data) const {
    447     DCHECK_EQ(inst_data, Fetch16(0));
    448     return static_cast<Code>(inst_data & 0xFF);
    449   }
    450 
    451   // Returns the opcode field of the instruction from the first 16 bits of instruction.
    452   Code Opcode() const {
    453     return Opcode(Fetch16(0));
    454   }
    455 
    456   void SetOpcode(Code opcode) {
    457     DCHECK_LT(static_cast<uint16_t>(opcode), 256u);
    458     uint16_t* insns = reinterpret_cast<uint16_t*>(this);
    459     insns[0] = (insns[0] & 0xff00) | static_cast<uint16_t>(opcode);
    460   }
    461 
    462   void SetVRegA_10x(uint8_t val) {
    463     DCHECK(FormatOf(Opcode()) == k10x);
    464     uint16_t* insns = reinterpret_cast<uint16_t*>(this);
    465     insns[0] = (val << 8) | (insns[0] & 0x00ff);
    466   }
    467 
    468   void SetVRegB_3rc(uint16_t val) {
    469     DCHECK(FormatOf(Opcode()) == k3rc);
    470     uint16_t* insns = reinterpret_cast<uint16_t*>(this);
    471     insns[1] = val;
    472   }
    473 
    474   void SetVRegB_35c(uint16_t val) {
    475     DCHECK(FormatOf(Opcode()) == k35c);
    476     uint16_t* insns = reinterpret_cast<uint16_t*>(this);
    477     insns[1] = val;
    478   }
    479 
    480   void SetVRegC_22c(uint16_t val) {
    481     DCHECK(FormatOf(Opcode()) == k22c);
    482     uint16_t* insns = reinterpret_cast<uint16_t*>(this);
    483     insns[1] = val;
    484   }
    485 
    486   void SetVRegA_21c(uint8_t val) {
    487     DCHECK(FormatOf(Opcode()) == k21c);
    488     uint16_t* insns = reinterpret_cast<uint16_t*>(this);
    489     insns[0] = (val << 8) | (insns[0] & 0x00ff);
    490   }
    491 
    492   void SetVRegB_21c(uint16_t val) {
    493     DCHECK(FormatOf(Opcode()) == k21c);
    494     uint16_t* insns = reinterpret_cast<uint16_t*>(this);
    495     insns[1] = val;
    496   }
    497 
    498   // Returns the format of the given opcode.
    499   static Format FormatOf(Code opcode) {
    500     return kInstructionFormats[opcode];
    501   }
    502 
    503   // Returns the index type of the given opcode.
    504   static IndexType IndexTypeOf(Code opcode) {
    505     return kInstructionIndexTypes[opcode];
    506   }
    507 
    508   // Returns the flags for the given opcode.
    509   static int FlagsOf(Code opcode) {
    510     return kInstructionFlags[opcode];
    511   }
    512 
    513   // Return the verify flags for the given opcode.
    514   static int VerifyFlagsOf(Code opcode) {
    515     return kInstructionVerifyFlags[opcode];
    516   }
    517 
    518   // Returns true if this instruction is a branch.
    519   bool IsBranch() const {
    520     return (kInstructionFlags[Opcode()] & kBranch) != 0;
    521   }
    522 
    523   // Returns true if this instruction is a unconditional branch.
    524   bool IsUnconditional() const {
    525     return (kInstructionFlags[Opcode()] & kUnconditional) != 0;
    526   }
    527 
    528   // Returns the branch offset if this instruction is a branch.
    529   int32_t GetTargetOffset() const;
    530 
    531   // Returns true if the instruction allows control flow to go to the following instruction.
    532   bool CanFlowThrough() const;
    533 
    534   // Returns true if the instruction is a quickened instruction.
    535   bool IsQuickened() const {
    536     return (kInstructionIndexTypes[Opcode()] == kIndexFieldOffset) ||
    537         (kInstructionIndexTypes[Opcode()] == kIndexVtableOffset);
    538   }
    539 
    540   // Returns true if this instruction is a switch.
    541   bool IsSwitch() const {
    542     return (kInstructionFlags[Opcode()] & kSwitch) != 0;
    543   }
    544 
    545   // Returns true if this instruction can throw.
    546   bool IsThrow() const {
    547     return (kInstructionFlags[Opcode()] & kThrow) != 0;
    548   }
    549 
    550   // Determine if the instruction is any of 'return' instructions.
    551   bool IsReturn() const {
    552     return (kInstructionFlags[Opcode()] & kReturn) != 0;
    553   }
    554 
    555   // Determine if this instruction ends execution of its basic block.
    556   bool IsBasicBlockEnd() const {
    557     return IsBranch() || IsReturn() || Opcode() == THROW;
    558   }
    559 
    560   // Determine if this instruction is an invoke.
    561   bool IsInvoke() const {
    562     return (kInstructionFlags[Opcode()] & kInvoke) != 0;
    563   }
    564 
    565   // Determine if this instruction is experimental.
    566   bool IsExperimental() const {
    567     return (kInstructionFlags[Opcode()] & kExperimental) != 0;
    568   }
    569 
    570   int GetVerifyTypeArgumentA() const {
    571     return (kInstructionVerifyFlags[Opcode()] & (kVerifyRegA | kVerifyRegAWide));
    572   }
    573 
    574   int GetVerifyTypeArgumentB() const {
    575     return (kInstructionVerifyFlags[Opcode()] & (kVerifyRegB | kVerifyRegBField |
    576         kVerifyRegBMethod | kVerifyRegBNewInstance | kVerifyRegBString | kVerifyRegBType |
    577         kVerifyRegBWide));
    578   }
    579 
    580   int GetVerifyTypeArgumentC() const {
    581     return (kInstructionVerifyFlags[Opcode()] & (kVerifyRegC | kVerifyRegCField |
    582         kVerifyRegCNewArray | kVerifyRegCType | kVerifyRegCWide));
    583   }
    584 
    585   int GetVerifyTypeArgumentH() const {
    586     return (kInstructionVerifyFlags[Opcode()] & kVerifyRegHPrototype);
    587   }
    588 
    589   int GetVerifyExtraFlags() const {
    590     return (kInstructionVerifyFlags[Opcode()] & (kVerifyArrayData | kVerifyBranchTarget |
    591         kVerifySwitchTargets | kVerifyVarArg | kVerifyVarArgNonZero | kVerifyVarArgRange |
    592         kVerifyVarArgRangeNonZero | kVerifyError));
    593   }
    594 
    595   bool GetVerifyIsRuntimeOnly() const {
    596     return (kInstructionVerifyFlags[Opcode()] & kVerifyRuntimeOnly) != 0;
    597   }
    598 
    599   // Get the dex PC of this instruction as a offset in code units from the beginning of insns.
    600   uint32_t GetDexPc(const uint16_t* insns) const {
    601     return (reinterpret_cast<const uint16_t*>(this) - insns);
    602   }
    603 
    604   // Dump decoded version of instruction
    605   std::string DumpString(const DexFile*) const;
    606 
    607   // Dump code_units worth of this instruction, padding to code_units for shorter instructions
    608   std::string DumpHex(size_t code_units) const;
    609 
    610   // Little-endian dump code_units worth of this instruction, padding to code_units for
    611   // shorter instructions
    612   std::string DumpHexLE(size_t instr_code_units) const;
    613 
    614   uint16_t Fetch16(size_t offset) const {
    615     const uint16_t* insns = reinterpret_cast<const uint16_t*>(this);
    616     return insns[offset];
    617   }
    618 
    619  private:
    620   size_t SizeInCodeUnitsComplexOpcode() const;
    621 
    622   uint32_t Fetch32(size_t offset) const {
    623     return (Fetch16(offset) | ((uint32_t) Fetch16(offset + 1) << 16));
    624   }
    625 
    626   uint4_t InstA() const {
    627     return InstA(Fetch16(0));
    628   }
    629 
    630   uint4_t InstB() const {
    631     return InstB(Fetch16(0));
    632   }
    633 
    634   uint8_t InstAA() const {
    635     return InstAA(Fetch16(0));
    636   }
    637 
    638   uint4_t InstA(uint16_t inst_data) const {
    639     DCHECK_EQ(inst_data, Fetch16(0));
    640     return static_cast<uint4_t>((inst_data >> 8) & 0x0f);
    641   }
    642 
    643   uint4_t InstB(uint16_t inst_data) const {
    644     DCHECK_EQ(inst_data, Fetch16(0));
    645     return static_cast<uint4_t>(inst_data >> 12);
    646   }
    647 
    648   uint8_t InstAA(uint16_t inst_data) const {
    649     DCHECK_EQ(inst_data, Fetch16(0));
    650     return static_cast<uint8_t>(inst_data >> 8);
    651   }
    652 
    653   static const char* const kInstructionNames[];
    654   static Format const kInstructionFormats[];
    655   static IndexType const kInstructionIndexTypes[];
    656   static int const kInstructionFlags[];
    657   static int const kInstructionVerifyFlags[];
    658   static int const kInstructionSizeInCodeUnits[];
    659   DISALLOW_IMPLICIT_CONSTRUCTORS(Instruction);
    660 };
    661 std::ostream& operator<<(std::ostream& os, const Instruction::Code& code);
    662 std::ostream& operator<<(std::ostream& os, const Instruction::Format& format);
    663 std::ostream& operator<<(std::ostream& os, const Instruction::Flags& flags);
    664 std::ostream& operator<<(std::ostream& os, const Instruction::VerifyFlag& vflags);
    665 
    666 }  // namespace art
    667 
    668 #endif  // ART_RUNTIME_DEX_INSTRUCTION_H_
    669