1 /* Disassembler interface for targets using CGEN. -*- C -*- 2 CGEN: Cpu tools GENerator 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN. 5 - the resultant file is machine generated, cgen-dis.in isn't 6 7 Copyright (C) 1996-2014 Free Software Foundation, Inc. 8 9 This file is part of libopcodes. 10 11 This library is free software; you can redistribute it and/or modify 12 it under the terms of the GNU General Public License as published by 13 the Free Software Foundation; either version 3, or (at your option) 14 any later version. 15 16 It is distributed in the hope that it will be useful, but WITHOUT 17 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 18 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 19 License for more details. 20 21 You should have received a copy of the GNU General Public License 22 along with this program; if not, write to the Free Software Foundation, Inc., 23 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 24 25 /* ??? Eventually more and more of this stuff can go to cpu-independent files. 26 Keep that in mind. */ 27 28 #include "sysdep.h" 29 #include <stdio.h> 30 #include "ansidecl.h" 31 #include "dis-asm.h" 32 #include "bfd.h" 33 #include "symcat.h" 34 #include "libiberty.h" 35 #include "m32c-desc.h" 36 #include "m32c-opc.h" 37 #include "opintl.h" 38 39 /* Default text to print if an instruction isn't recognized. */ 40 #define UNKNOWN_INSN_MSG _("*unknown*") 41 42 static void print_normal 43 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 44 static void print_address 45 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; 46 static void print_keyword 47 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; 48 static void print_insn_normal 49 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); 50 static int print_insn 51 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); 52 static int default_print_insn 53 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; 54 static int read_insn 55 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, 56 unsigned long *); 57 58 /* -- disassembler routines inserted here. */ 60 61 /* -- dis.c */ 62 63 #include "elf/m32c.h" 64 #include "elf-bfd.h" 65 66 /* Always print the short insn format suffix as ':<char>'. */ 67 68 static void 69 print_suffix (void * dis_info, char suffix) 70 { 71 disassemble_info *info = dis_info; 72 73 (*info->fprintf_func) (info->stream, ":%c", suffix); 74 } 75 76 static void 77 print_S (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 78 void * dis_info, 79 long value ATTRIBUTE_UNUSED, 80 unsigned int attrs ATTRIBUTE_UNUSED, 81 bfd_vma pc ATTRIBUTE_UNUSED, 82 int length ATTRIBUTE_UNUSED) 83 { 84 print_suffix (dis_info, 's'); 85 } 86 87 88 static void 89 print_G (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 90 void * dis_info, 91 long value ATTRIBUTE_UNUSED, 92 unsigned int attrs ATTRIBUTE_UNUSED, 93 bfd_vma pc ATTRIBUTE_UNUSED, 94 int length ATTRIBUTE_UNUSED) 95 { 96 print_suffix (dis_info, 'g'); 97 } 98 99 static void 100 print_Q (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 101 void * dis_info, 102 long value ATTRIBUTE_UNUSED, 103 unsigned int attrs ATTRIBUTE_UNUSED, 104 bfd_vma pc ATTRIBUTE_UNUSED, 105 int length ATTRIBUTE_UNUSED) 106 { 107 print_suffix (dis_info, 'q'); 108 } 109 110 static void 111 print_Z (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 112 void * dis_info, 113 long value ATTRIBUTE_UNUSED, 114 unsigned int attrs ATTRIBUTE_UNUSED, 115 bfd_vma pc ATTRIBUTE_UNUSED, 116 int length ATTRIBUTE_UNUSED) 117 { 118 print_suffix (dis_info, 'z'); 119 } 120 121 /* Print the empty suffix. */ 122 123 static void 124 print_X (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 125 void * dis_info ATTRIBUTE_UNUSED, 126 long value ATTRIBUTE_UNUSED, 127 unsigned int attrs ATTRIBUTE_UNUSED, 128 bfd_vma pc ATTRIBUTE_UNUSED, 129 int length ATTRIBUTE_UNUSED) 130 { 131 return; 132 } 133 134 static void 135 print_r0l_r0h (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 136 void * dis_info, 137 long value, 138 unsigned int attrs ATTRIBUTE_UNUSED, 139 bfd_vma pc ATTRIBUTE_UNUSED, 140 int length ATTRIBUTE_UNUSED) 141 { 142 disassemble_info *info = dis_info; 143 144 if (value == 0) 145 (*info->fprintf_func) (info->stream, "r0h,r0l"); 146 else 147 (*info->fprintf_func) (info->stream, "r0l,r0h"); 148 } 149 150 static void 151 print_unsigned_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 152 void * dis_info, 153 unsigned long value, 154 unsigned int attrs ATTRIBUTE_UNUSED, 155 bfd_vma pc ATTRIBUTE_UNUSED, 156 int length ATTRIBUTE_UNUSED) 157 { 158 disassemble_info *info = dis_info; 159 160 (*info->fprintf_func) (info->stream, "%ld,0x%lx", value & 0x7, value >> 3); 161 } 162 163 static void 164 print_signed_bitbase (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 165 void * dis_info, 166 signed long value, 167 unsigned int attrs ATTRIBUTE_UNUSED, 168 bfd_vma pc ATTRIBUTE_UNUSED, 169 int length ATTRIBUTE_UNUSED) 170 { 171 disassemble_info *info = dis_info; 172 173 (*info->fprintf_func) (info->stream, "%ld,%ld", value & 0x7, value >> 3); 174 } 175 176 static void 177 print_size (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 178 void * dis_info, 179 long value ATTRIBUTE_UNUSED, 180 unsigned int attrs ATTRIBUTE_UNUSED, 181 bfd_vma pc ATTRIBUTE_UNUSED, 182 int length ATTRIBUTE_UNUSED) 183 { 184 /* Always print the size as '.w'. */ 185 disassemble_info *info = dis_info; 186 187 (*info->fprintf_func) (info->stream, ".w"); 188 } 189 190 #define POP 0 191 #define PUSH 1 192 193 static void print_pop_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 194 static void print_push_regset (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 195 196 /* Print a set of registers, R0,R1,A0,A1,SB,FB. */ 197 198 static void 199 print_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 200 void * dis_info, 201 long value, 202 unsigned int attrs ATTRIBUTE_UNUSED, 203 bfd_vma pc ATTRIBUTE_UNUSED, 204 int length ATTRIBUTE_UNUSED, 205 int push) 206 { 207 static char * m16c_register_names [] = 208 { 209 "r0", "r1", "r2", "r3", "a0", "a1", "sb", "fb" 210 }; 211 disassemble_info *info = dis_info; 212 int mask; 213 int reg_index = 0; 214 char* comma = ""; 215 216 if (push) 217 mask = 0x80; 218 else 219 mask = 1; 220 221 if (value & mask) 222 { 223 (*info->fprintf_func) (info->stream, "%s", m16c_register_names [0]); 224 comma = ","; 225 } 226 227 for (reg_index = 1; reg_index <= 7; ++reg_index) 228 { 229 if (push) 230 mask >>= 1; 231 else 232 mask <<= 1; 233 234 if (value & mask) 235 { 236 (*info->fprintf_func) (info->stream, "%s%s", comma, 237 m16c_register_names [reg_index]); 238 comma = ","; 239 } 240 } 241 } 242 243 static void 244 print_pop_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 245 void * dis_info, 246 long value, 247 unsigned int attrs ATTRIBUTE_UNUSED, 248 bfd_vma pc ATTRIBUTE_UNUSED, 249 int length ATTRIBUTE_UNUSED) 250 { 251 print_regset (cd, dis_info, value, attrs, pc, length, POP); 252 } 253 254 static void 255 print_push_regset (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 256 void * dis_info, 257 long value, 258 unsigned int attrs ATTRIBUTE_UNUSED, 259 bfd_vma pc ATTRIBUTE_UNUSED, 260 int length ATTRIBUTE_UNUSED) 261 { 262 print_regset (cd, dis_info, value, attrs, pc, length, PUSH); 263 } 264 265 static void 266 print_signed4n (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 267 void * dis_info, 268 signed long value, 269 unsigned int attrs ATTRIBUTE_UNUSED, 270 bfd_vma pc ATTRIBUTE_UNUSED, 271 int length ATTRIBUTE_UNUSED) 272 { 273 disassemble_info *info = dis_info; 274 275 (*info->fprintf_func) (info->stream, "%ld", -value); 276 } 277 278 void m32c_cgen_print_operand 279 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); 280 281 /* Main entry point for printing operands. 282 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement 283 of dis-asm.h on cgen.h. 284 285 This function is basically just a big switch statement. Earlier versions 286 used tables to look up the function to use, but 287 - if the table contains both assembler and disassembler functions then 288 the disassembler contains much of the assembler and vice-versa, 289 - there's a lot of inlining possibilities as things grow, 290 - using a switch statement avoids the function call overhead. 291 292 This function could be moved into `print_insn_normal', but keeping it 293 separate makes clear the interface between `print_insn_normal' and each of 294 the handlers. */ 295 296 void 297 m32c_cgen_print_operand (CGEN_CPU_DESC cd, 298 int opindex, 299 void * xinfo, 300 CGEN_FIELDS *fields, 301 void const *attrs ATTRIBUTE_UNUSED, 302 bfd_vma pc, 303 int length) 304 { 305 disassemble_info *info = (disassemble_info *) xinfo; 306 307 switch (opindex) 308 { 309 case M32C_OPERAND_A0 : 310 print_keyword (cd, info, & m32c_cgen_opval_h_a0, 0, 0); 311 break; 312 case M32C_OPERAND_A1 : 313 print_keyword (cd, info, & m32c_cgen_opval_h_a1, 0, 0); 314 break; 315 case M32C_OPERAND_AN16_PUSH_S : 316 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_4_1, 0); 317 break; 318 case M32C_OPERAND_BIT16AN : 319 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst16_an, 0); 320 break; 321 case M32C_OPERAND_BIT16RN : 322 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0); 323 break; 324 case M32C_OPERAND_BIT3_S : 325 print_normal (cd, info, fields->f_imm3_S, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 326 break; 327 case M32C_OPERAND_BIT32ANPREFIXED : 328 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0); 329 break; 330 case M32C_OPERAND_BIT32ANUNPREFIXED : 331 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); 332 break; 333 case M32C_OPERAND_BIT32RNPREFIXED : 334 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_prefixed_QI, 0); 335 break; 336 case M32C_OPERAND_BIT32RNUNPREFIXED : 337 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0); 338 break; 339 case M32C_OPERAND_BITBASE16_16_S8 : 340 print_signed_bitbase (cd, info, fields->f_dsp_16_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 341 break; 342 case M32C_OPERAND_BITBASE16_16_U16 : 343 print_unsigned_bitbase (cd, info, fields->f_dsp_16_u16, 0, pc, length); 344 break; 345 case M32C_OPERAND_BITBASE16_16_U8 : 346 print_unsigned_bitbase (cd, info, fields->f_dsp_16_u8, 0, pc, length); 347 break; 348 case M32C_OPERAND_BITBASE16_8_U11_S : 349 print_unsigned_bitbase (cd, info, fields->f_bitbase16_u11_S, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 350 break; 351 case M32C_OPERAND_BITBASE32_16_S11_UNPREFIXED : 352 print_signed_bitbase (cd, info, fields->f_bitbase32_16_s11_unprefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 353 break; 354 case M32C_OPERAND_BITBASE32_16_S19_UNPREFIXED : 355 print_signed_bitbase (cd, info, fields->f_bitbase32_16_s19_unprefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 356 break; 357 case M32C_OPERAND_BITBASE32_16_U11_UNPREFIXED : 358 print_unsigned_bitbase (cd, info, fields->f_bitbase32_16_u11_unprefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 359 break; 360 case M32C_OPERAND_BITBASE32_16_U19_UNPREFIXED : 361 print_unsigned_bitbase (cd, info, fields->f_bitbase32_16_u19_unprefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 362 break; 363 case M32C_OPERAND_BITBASE32_16_U27_UNPREFIXED : 364 print_unsigned_bitbase (cd, info, fields->f_bitbase32_16_u27_unprefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 365 break; 366 case M32C_OPERAND_BITBASE32_24_S11_PREFIXED : 367 print_signed_bitbase (cd, info, fields->f_bitbase32_24_s11_prefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 368 break; 369 case M32C_OPERAND_BITBASE32_24_S19_PREFIXED : 370 print_signed_bitbase (cd, info, fields->f_bitbase32_24_s19_prefixed, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 371 break; 372 case M32C_OPERAND_BITBASE32_24_U11_PREFIXED : 373 print_unsigned_bitbase (cd, info, fields->f_bitbase32_24_u11_prefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 374 break; 375 case M32C_OPERAND_BITBASE32_24_U19_PREFIXED : 376 print_unsigned_bitbase (cd, info, fields->f_bitbase32_24_u19_prefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 377 break; 378 case M32C_OPERAND_BITBASE32_24_U27_PREFIXED : 379 print_unsigned_bitbase (cd, info, fields->f_bitbase32_24_u27_prefixed, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 380 break; 381 case M32C_OPERAND_BITNO16R : 382 print_normal (cd, info, fields->f_dsp_16_u8, 0, pc, length); 383 break; 384 case M32C_OPERAND_BITNO32PREFIXED : 385 print_normal (cd, info, fields->f_bitno32_prefixed, 0, pc, length); 386 break; 387 case M32C_OPERAND_BITNO32UNPREFIXED : 388 print_normal (cd, info, fields->f_bitno32_unprefixed, 0, pc, length); 389 break; 390 case M32C_OPERAND_DSP_10_U6 : 391 print_normal (cd, info, fields->f_dsp_10_u6, 0, pc, length); 392 break; 393 case M32C_OPERAND_DSP_16_S16 : 394 print_normal (cd, info, fields->f_dsp_16_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 395 break; 396 case M32C_OPERAND_DSP_16_S8 : 397 print_normal (cd, info, fields->f_dsp_16_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 398 break; 399 case M32C_OPERAND_DSP_16_U16 : 400 print_normal (cd, info, fields->f_dsp_16_u16, 0, pc, length); 401 break; 402 case M32C_OPERAND_DSP_16_U20 : 403 print_normal (cd, info, fields->f_dsp_16_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 404 break; 405 case M32C_OPERAND_DSP_16_U24 : 406 print_normal (cd, info, fields->f_dsp_16_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 407 break; 408 case M32C_OPERAND_DSP_16_U8 : 409 print_normal (cd, info, fields->f_dsp_16_u8, 0, pc, length); 410 break; 411 case M32C_OPERAND_DSP_24_S16 : 412 print_normal (cd, info, fields->f_dsp_24_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 413 break; 414 case M32C_OPERAND_DSP_24_S8 : 415 print_normal (cd, info, fields->f_dsp_24_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 416 break; 417 case M32C_OPERAND_DSP_24_U16 : 418 print_normal (cd, info, fields->f_dsp_24_u16, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 419 break; 420 case M32C_OPERAND_DSP_24_U20 : 421 print_normal (cd, info, fields->f_dsp_24_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 422 break; 423 case M32C_OPERAND_DSP_24_U24 : 424 print_normal (cd, info, fields->f_dsp_24_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 425 break; 426 case M32C_OPERAND_DSP_24_U8 : 427 print_normal (cd, info, fields->f_dsp_24_u8, 0, pc, length); 428 break; 429 case M32C_OPERAND_DSP_32_S16 : 430 print_normal (cd, info, fields->f_dsp_32_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 431 break; 432 case M32C_OPERAND_DSP_32_S8 : 433 print_normal (cd, info, fields->f_dsp_32_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 434 break; 435 case M32C_OPERAND_DSP_32_U16 : 436 print_normal (cd, info, fields->f_dsp_32_u16, 0, pc, length); 437 break; 438 case M32C_OPERAND_DSP_32_U20 : 439 print_normal (cd, info, fields->f_dsp_32_u24, 0, pc, length); 440 break; 441 case M32C_OPERAND_DSP_32_U24 : 442 print_normal (cd, info, fields->f_dsp_32_u24, 0, pc, length); 443 break; 444 case M32C_OPERAND_DSP_32_U8 : 445 print_normal (cd, info, fields->f_dsp_32_u8, 0, pc, length); 446 break; 447 case M32C_OPERAND_DSP_40_S16 : 448 print_normal (cd, info, fields->f_dsp_40_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 449 break; 450 case M32C_OPERAND_DSP_40_S8 : 451 print_normal (cd, info, fields->f_dsp_40_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 452 break; 453 case M32C_OPERAND_DSP_40_U16 : 454 print_normal (cd, info, fields->f_dsp_40_u16, 0, pc, length); 455 break; 456 case M32C_OPERAND_DSP_40_U20 : 457 print_normal (cd, info, fields->f_dsp_40_u20, 0, pc, length); 458 break; 459 case M32C_OPERAND_DSP_40_U24 : 460 print_normal (cd, info, fields->f_dsp_40_u24, 0, pc, length); 461 break; 462 case M32C_OPERAND_DSP_40_U8 : 463 print_normal (cd, info, fields->f_dsp_40_u8, 0, pc, length); 464 break; 465 case M32C_OPERAND_DSP_48_S16 : 466 print_normal (cd, info, fields->f_dsp_48_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 467 break; 468 case M32C_OPERAND_DSP_48_S8 : 469 print_normal (cd, info, fields->f_dsp_48_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 470 break; 471 case M32C_OPERAND_DSP_48_U16 : 472 print_normal (cd, info, fields->f_dsp_48_u16, 0, pc, length); 473 break; 474 case M32C_OPERAND_DSP_48_U20 : 475 print_normal (cd, info, fields->f_dsp_48_u20, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 476 break; 477 case M32C_OPERAND_DSP_48_U24 : 478 print_normal (cd, info, fields->f_dsp_48_u24, 0|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 479 break; 480 case M32C_OPERAND_DSP_48_U8 : 481 print_normal (cd, info, fields->f_dsp_48_u8, 0, pc, length); 482 break; 483 case M32C_OPERAND_DSP_8_S24 : 484 print_normal (cd, info, fields->f_dsp_8_s24, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 485 break; 486 case M32C_OPERAND_DSP_8_S8 : 487 print_normal (cd, info, fields->f_dsp_8_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 488 break; 489 case M32C_OPERAND_DSP_8_U16 : 490 print_normal (cd, info, fields->f_dsp_8_u16, 0, pc, length); 491 break; 492 case M32C_OPERAND_DSP_8_U24 : 493 print_normal (cd, info, fields->f_dsp_8_u24, 0, pc, length); 494 break; 495 case M32C_OPERAND_DSP_8_U6 : 496 print_normal (cd, info, fields->f_dsp_8_u6, 0, pc, length); 497 break; 498 case M32C_OPERAND_DSP_8_U8 : 499 print_normal (cd, info, fields->f_dsp_8_u8, 0, pc, length); 500 break; 501 case M32C_OPERAND_DST16AN : 502 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst16_an, 0); 503 break; 504 case M32C_OPERAND_DST16AN_S : 505 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst16_an_s, 0); 506 break; 507 case M32C_OPERAND_DST16ANHI : 508 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst16_an, 0); 509 break; 510 case M32C_OPERAND_DST16ANQI : 511 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst16_an, 0); 512 break; 513 case M32C_OPERAND_DST16ANQI_S : 514 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst16_rn_QI_s, 0); 515 break; 516 case M32C_OPERAND_DST16ANSI : 517 print_keyword (cd, info, & m32c_cgen_opval_h_ar_SI, fields->f_dst16_an, 0); 518 break; 519 case M32C_OPERAND_DST16RNEXTQI : 520 print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_QI, fields->f_dst16_rn_ext, 0); 521 break; 522 case M32C_OPERAND_DST16RNHI : 523 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst16_rn, 0); 524 break; 525 case M32C_OPERAND_DST16RNQI : 526 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst16_rn, 0); 527 break; 528 case M32C_OPERAND_DST16RNQI_S : 529 print_keyword (cd, info, & m32c_cgen_opval_h_r0l_r0h, fields->f_dst16_rn_QI_s, 0); 530 break; 531 case M32C_OPERAND_DST16RNSI : 532 print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst16_rn, 0); 533 break; 534 case M32C_OPERAND_DST32ANEXTUNPREFIXED : 535 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); 536 break; 537 case M32C_OPERAND_DST32ANPREFIXED : 538 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0); 539 break; 540 case M32C_OPERAND_DST32ANPREFIXEDHI : 541 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst32_an_prefixed, 0); 542 break; 543 case M32C_OPERAND_DST32ANPREFIXEDQI : 544 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst32_an_prefixed, 0); 545 break; 546 case M32C_OPERAND_DST32ANPREFIXEDSI : 547 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_prefixed, 0); 548 break; 549 case M32C_OPERAND_DST32ANUNPREFIXED : 550 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); 551 break; 552 case M32C_OPERAND_DST32ANUNPREFIXEDHI : 553 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_dst32_an_unprefixed, 0); 554 break; 555 case M32C_OPERAND_DST32ANUNPREFIXEDQI : 556 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_dst32_an_unprefixed, 0); 557 break; 558 case M32C_OPERAND_DST32ANUNPREFIXEDSI : 559 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_dst32_an_unprefixed, 0); 560 break; 561 case M32C_OPERAND_DST32R0HI_S : 562 print_keyword (cd, info, & m32c_cgen_opval_h_r0, 0, 0); 563 break; 564 case M32C_OPERAND_DST32R0QI_S : 565 print_keyword (cd, info, & m32c_cgen_opval_h_r0l, 0, 0); 566 break; 567 case M32C_OPERAND_DST32RNEXTUNPREFIXEDHI : 568 print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_HI, fields->f_dst32_rn_ext_unprefixed, 0); 569 break; 570 case M32C_OPERAND_DST32RNEXTUNPREFIXEDQI : 571 print_keyword (cd, info, & m32c_cgen_opval_h_gr_ext_QI, fields->f_dst32_rn_ext_unprefixed, 0); 572 break; 573 case M32C_OPERAND_DST32RNPREFIXEDHI : 574 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst32_rn_prefixed_HI, 0); 575 break; 576 case M32C_OPERAND_DST32RNPREFIXEDQI : 577 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_prefixed_QI, 0); 578 break; 579 case M32C_OPERAND_DST32RNPREFIXEDSI : 580 print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst32_rn_prefixed_SI, 0); 581 break; 582 case M32C_OPERAND_DST32RNUNPREFIXEDHI : 583 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_dst32_rn_unprefixed_HI, 0); 584 break; 585 case M32C_OPERAND_DST32RNUNPREFIXEDQI : 586 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_dst32_rn_unprefixed_QI, 0); 587 break; 588 case M32C_OPERAND_DST32RNUNPREFIXEDSI : 589 print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_dst32_rn_unprefixed_SI, 0); 590 break; 591 case M32C_OPERAND_G : 592 print_G (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 593 break; 594 case M32C_OPERAND_IMM_12_S4 : 595 print_normal (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 596 break; 597 case M32C_OPERAND_IMM_12_S4N : 598 print_signed4n (cd, info, fields->f_imm_12_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 599 break; 600 case M32C_OPERAND_IMM_13_U3 : 601 print_normal (cd, info, fields->f_imm_13_u3, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 602 break; 603 case M32C_OPERAND_IMM_16_HI : 604 print_normal (cd, info, fields->f_dsp_16_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 605 break; 606 case M32C_OPERAND_IMM_16_QI : 607 print_normal (cd, info, fields->f_dsp_16_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 608 break; 609 case M32C_OPERAND_IMM_16_SI : 610 print_normal (cd, info, fields->f_dsp_16_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 611 break; 612 case M32C_OPERAND_IMM_20_S4 : 613 print_normal (cd, info, fields->f_imm_20_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 614 break; 615 case M32C_OPERAND_IMM_24_HI : 616 print_normal (cd, info, fields->f_dsp_24_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 617 break; 618 case M32C_OPERAND_IMM_24_QI : 619 print_normal (cd, info, fields->f_dsp_24_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 620 break; 621 case M32C_OPERAND_IMM_24_SI : 622 print_normal (cd, info, fields->f_dsp_24_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 623 break; 624 case M32C_OPERAND_IMM_32_HI : 625 print_normal (cd, info, fields->f_dsp_32_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 626 break; 627 case M32C_OPERAND_IMM_32_QI : 628 print_normal (cd, info, fields->f_dsp_32_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 629 break; 630 case M32C_OPERAND_IMM_32_SI : 631 print_normal (cd, info, fields->f_dsp_32_s32, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 632 break; 633 case M32C_OPERAND_IMM_40_HI : 634 print_normal (cd, info, fields->f_dsp_40_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 635 break; 636 case M32C_OPERAND_IMM_40_QI : 637 print_normal (cd, info, fields->f_dsp_40_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 638 break; 639 case M32C_OPERAND_IMM_40_SI : 640 print_normal (cd, info, fields->f_dsp_40_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 641 break; 642 case M32C_OPERAND_IMM_48_HI : 643 print_normal (cd, info, fields->f_dsp_48_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 644 break; 645 case M32C_OPERAND_IMM_48_QI : 646 print_normal (cd, info, fields->f_dsp_48_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 647 break; 648 case M32C_OPERAND_IMM_48_SI : 649 print_normal (cd, info, fields->f_dsp_48_s32, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 650 break; 651 case M32C_OPERAND_IMM_56_HI : 652 print_normal (cd, info, fields->f_dsp_56_s16, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 653 break; 654 case M32C_OPERAND_IMM_56_QI : 655 print_normal (cd, info, fields->f_dsp_56_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 656 break; 657 case M32C_OPERAND_IMM_64_HI : 658 print_normal (cd, info, fields->f_dsp_64_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 659 break; 660 case M32C_OPERAND_IMM_8_HI : 661 print_normal (cd, info, fields->f_dsp_8_s16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 662 break; 663 case M32C_OPERAND_IMM_8_QI : 664 print_normal (cd, info, fields->f_dsp_8_s8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 665 break; 666 case M32C_OPERAND_IMM_8_S4 : 667 print_normal (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 668 break; 669 case M32C_OPERAND_IMM_8_S4N : 670 print_signed4n (cd, info, fields->f_imm_8_s4, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 671 break; 672 case M32C_OPERAND_IMM_SH_12_S4 : 673 print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_12_s4, 0); 674 break; 675 case M32C_OPERAND_IMM_SH_20_S4 : 676 print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_20_s4, 0); 677 break; 678 case M32C_OPERAND_IMM_SH_8_S4 : 679 print_keyword (cd, info, & m32c_cgen_opval_h_shimm, fields->f_imm_8_s4, 0); 680 break; 681 case M32C_OPERAND_IMM1_S : 682 print_normal (cd, info, fields->f_imm1_S, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 683 break; 684 case M32C_OPERAND_IMM3_S : 685 print_normal (cd, info, fields->f_imm3_S, 0|(1<<CGEN_OPERAND_SIGNED)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 686 break; 687 case M32C_OPERAND_LAB_16_8 : 688 print_address (cd, info, fields->f_lab_16_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 689 break; 690 case M32C_OPERAND_LAB_24_8 : 691 print_address (cd, info, fields->f_lab_24_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 692 break; 693 case M32C_OPERAND_LAB_32_8 : 694 print_address (cd, info, fields->f_lab_32_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 695 break; 696 case M32C_OPERAND_LAB_40_8 : 697 print_address (cd, info, fields->f_lab_40_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 698 break; 699 case M32C_OPERAND_LAB_5_3 : 700 print_address (cd, info, fields->f_lab_5_3, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 701 break; 702 case M32C_OPERAND_LAB_8_16 : 703 print_address (cd, info, fields->f_lab_8_16, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_SIGN_OPT)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 704 break; 705 case M32C_OPERAND_LAB_8_24 : 706 print_address (cd, info, fields->f_lab_8_24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); 707 break; 708 case M32C_OPERAND_LAB_8_8 : 709 print_address (cd, info, fields->f_lab_8_8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 710 break; 711 case M32C_OPERAND_LAB32_JMP_S : 712 print_address (cd, info, fields->f_lab32_jmp_s, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_PCREL_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 713 break; 714 case M32C_OPERAND_Q : 715 print_Q (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 716 break; 717 case M32C_OPERAND_R0 : 718 print_keyword (cd, info, & m32c_cgen_opval_h_r0, 0, 0); 719 break; 720 case M32C_OPERAND_R0H : 721 print_keyword (cd, info, & m32c_cgen_opval_h_r0h, 0, 0); 722 break; 723 case M32C_OPERAND_R0L : 724 print_keyword (cd, info, & m32c_cgen_opval_h_r0l, 0, 0); 725 break; 726 case M32C_OPERAND_R1 : 727 print_keyword (cd, info, & m32c_cgen_opval_h_r1, 0, 0); 728 break; 729 case M32C_OPERAND_R1R2R0 : 730 print_keyword (cd, info, & m32c_cgen_opval_h_r1r2r0, 0, 0); 731 break; 732 case M32C_OPERAND_R2 : 733 print_keyword (cd, info, & m32c_cgen_opval_h_r2, 0, 0); 734 break; 735 case M32C_OPERAND_R2R0 : 736 print_keyword (cd, info, & m32c_cgen_opval_h_r2r0, 0, 0); 737 break; 738 case M32C_OPERAND_R3 : 739 print_keyword (cd, info, & m32c_cgen_opval_h_r3, 0, 0); 740 break; 741 case M32C_OPERAND_R3R1 : 742 print_keyword (cd, info, & m32c_cgen_opval_h_r3r1, 0, 0); 743 break; 744 case M32C_OPERAND_REGSETPOP : 745 print_pop_regset (cd, info, fields->f_8_8, 0, pc, length); 746 break; 747 case M32C_OPERAND_REGSETPUSH : 748 print_push_regset (cd, info, fields->f_8_8, 0, pc, length); 749 break; 750 case M32C_OPERAND_RN16_PUSH_S : 751 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_4_1, 0); 752 break; 753 case M32C_OPERAND_S : 754 print_S (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 755 break; 756 case M32C_OPERAND_SRC16AN : 757 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src16_an, 0); 758 break; 759 case M32C_OPERAND_SRC16ANHI : 760 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src16_an, 0); 761 break; 762 case M32C_OPERAND_SRC16ANQI : 763 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src16_an, 0); 764 break; 765 case M32C_OPERAND_SRC16RNHI : 766 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src16_rn, 0); 767 break; 768 case M32C_OPERAND_SRC16RNQI : 769 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src16_rn, 0); 770 break; 771 case M32C_OPERAND_SRC32ANPREFIXED : 772 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_prefixed, 0); 773 break; 774 case M32C_OPERAND_SRC32ANPREFIXEDHI : 775 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src32_an_prefixed, 0); 776 break; 777 case M32C_OPERAND_SRC32ANPREFIXEDQI : 778 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src32_an_prefixed, 0); 779 break; 780 case M32C_OPERAND_SRC32ANPREFIXEDSI : 781 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_prefixed, 0); 782 break; 783 case M32C_OPERAND_SRC32ANUNPREFIXED : 784 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_unprefixed, 0); 785 break; 786 case M32C_OPERAND_SRC32ANUNPREFIXEDHI : 787 print_keyword (cd, info, & m32c_cgen_opval_h_ar_HI, fields->f_src32_an_unprefixed, 0); 788 break; 789 case M32C_OPERAND_SRC32ANUNPREFIXEDQI : 790 print_keyword (cd, info, & m32c_cgen_opval_h_ar_QI, fields->f_src32_an_unprefixed, 0); 791 break; 792 case M32C_OPERAND_SRC32ANUNPREFIXEDSI : 793 print_keyword (cd, info, & m32c_cgen_opval_h_ar, fields->f_src32_an_unprefixed, 0); 794 break; 795 case M32C_OPERAND_SRC32RNPREFIXEDHI : 796 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src32_rn_prefixed_HI, 0); 797 break; 798 case M32C_OPERAND_SRC32RNPREFIXEDQI : 799 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src32_rn_prefixed_QI, 0); 800 break; 801 case M32C_OPERAND_SRC32RNPREFIXEDSI : 802 print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_src32_rn_prefixed_SI, 0); 803 break; 804 case M32C_OPERAND_SRC32RNUNPREFIXEDHI : 805 print_keyword (cd, info, & m32c_cgen_opval_h_gr_HI, fields->f_src32_rn_unprefixed_HI, 0); 806 break; 807 case M32C_OPERAND_SRC32RNUNPREFIXEDQI : 808 print_keyword (cd, info, & m32c_cgen_opval_h_gr_QI, fields->f_src32_rn_unprefixed_QI, 0); 809 break; 810 case M32C_OPERAND_SRC32RNUNPREFIXEDSI : 811 print_keyword (cd, info, & m32c_cgen_opval_h_gr_SI, fields->f_src32_rn_unprefixed_SI, 0); 812 break; 813 case M32C_OPERAND_SRCDST16_R0L_R0H_S_NORMAL : 814 print_r0l_r0h (cd, info, fields->f_5_1, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 815 break; 816 case M32C_OPERAND_X : 817 print_X (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 818 break; 819 case M32C_OPERAND_Z : 820 print_Z (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 821 break; 822 case M32C_OPERAND_COND16_16 : 823 print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_16_u8, 0); 824 break; 825 case M32C_OPERAND_COND16_24 : 826 print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_24_u8, 0); 827 break; 828 case M32C_OPERAND_COND16_32 : 829 print_keyword (cd, info, & m32c_cgen_opval_h_cond16, fields->f_dsp_32_u8, 0); 830 break; 831 case M32C_OPERAND_COND16C : 832 print_keyword (cd, info, & m32c_cgen_opval_h_cond16c, fields->f_cond16, 0); 833 break; 834 case M32C_OPERAND_COND16J : 835 print_keyword (cd, info, & m32c_cgen_opval_h_cond16j, fields->f_cond16, 0); 836 break; 837 case M32C_OPERAND_COND16J5 : 838 print_keyword (cd, info, & m32c_cgen_opval_h_cond16j_5, fields->f_cond16j_5, 0); 839 break; 840 case M32C_OPERAND_COND32 : 841 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond32, 0|(1<<CGEN_OPERAND_VIRTUAL)); 842 break; 843 case M32C_OPERAND_COND32_16 : 844 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_16_u8, 0); 845 break; 846 case M32C_OPERAND_COND32_24 : 847 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_24_u8, 0); 848 break; 849 case M32C_OPERAND_COND32_32 : 850 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_32_u8, 0); 851 break; 852 case M32C_OPERAND_COND32_40 : 853 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_dsp_40_u8, 0); 854 break; 855 case M32C_OPERAND_COND32J : 856 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond32j, 0|(1<<CGEN_OPERAND_VIRTUAL)); 857 break; 858 case M32C_OPERAND_CR1_PREFIXED_32 : 859 print_keyword (cd, info, & m32c_cgen_opval_h_cr1_32, fields->f_21_3, 0); 860 break; 861 case M32C_OPERAND_CR1_UNPREFIXED_32 : 862 print_keyword (cd, info, & m32c_cgen_opval_h_cr1_32, fields->f_13_3, 0); 863 break; 864 case M32C_OPERAND_CR16 : 865 print_keyword (cd, info, & m32c_cgen_opval_h_cr_16, fields->f_9_3, 0); 866 break; 867 case M32C_OPERAND_CR2_32 : 868 print_keyword (cd, info, & m32c_cgen_opval_h_cr2_32, fields->f_13_3, 0); 869 break; 870 case M32C_OPERAND_CR3_PREFIXED_32 : 871 print_keyword (cd, info, & m32c_cgen_opval_h_cr3_32, fields->f_21_3, 0); 872 break; 873 case M32C_OPERAND_CR3_UNPREFIXED_32 : 874 print_keyword (cd, info, & m32c_cgen_opval_h_cr3_32, fields->f_13_3, 0); 875 break; 876 case M32C_OPERAND_FLAGS16 : 877 print_keyword (cd, info, & m32c_cgen_opval_h_flags, fields->f_9_3, 0); 878 break; 879 case M32C_OPERAND_FLAGS32 : 880 print_keyword (cd, info, & m32c_cgen_opval_h_flags, fields->f_13_3, 0); 881 break; 882 case M32C_OPERAND_SCCOND32 : 883 print_keyword (cd, info, & m32c_cgen_opval_h_cond32, fields->f_cond16, 0); 884 break; 885 case M32C_OPERAND_SIZE : 886 print_size (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 887 break; 888 889 default : 890 /* xgettext:c-format */ 891 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), 892 opindex); 893 abort (); 894 } 895 } 896 897 cgen_print_fn * const m32c_cgen_print_handlers[] = 898 { 899 print_insn_normal, 900 }; 901 902 903 void 904 m32c_cgen_init_dis (CGEN_CPU_DESC cd) 905 { 906 m32c_cgen_init_opcode_table (cd); 907 m32c_cgen_init_ibld_table (cd); 908 cd->print_handlers = & m32c_cgen_print_handlers[0]; 909 cd->print_operand = m32c_cgen_print_operand; 910 } 911 912 913 /* Default print handler. */ 915 916 static void 917 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 918 void *dis_info, 919 long value, 920 unsigned int attrs, 921 bfd_vma pc ATTRIBUTE_UNUSED, 922 int length ATTRIBUTE_UNUSED) 923 { 924 disassemble_info *info = (disassemble_info *) dis_info; 925 926 /* Print the operand as directed by the attributes. */ 927 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 928 ; /* nothing to do */ 929 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 930 (*info->fprintf_func) (info->stream, "%ld", value); 931 else 932 (*info->fprintf_func) (info->stream, "0x%lx", value); 933 } 934 935 /* Default address handler. */ 936 937 static void 938 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 939 void *dis_info, 940 bfd_vma value, 941 unsigned int attrs, 942 bfd_vma pc ATTRIBUTE_UNUSED, 943 int length ATTRIBUTE_UNUSED) 944 { 945 disassemble_info *info = (disassemble_info *) dis_info; 946 947 /* Print the operand as directed by the attributes. */ 948 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 949 ; /* Nothing to do. */ 950 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) 951 (*info->print_address_func) (value, info); 952 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) 953 (*info->print_address_func) (value, info); 954 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 955 (*info->fprintf_func) (info->stream, "%ld", (long) value); 956 else 957 (*info->fprintf_func) (info->stream, "0x%lx", (long) value); 958 } 959 960 /* Keyword print handler. */ 961 962 static void 963 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 964 void *dis_info, 965 CGEN_KEYWORD *keyword_table, 966 long value, 967 unsigned int attrs ATTRIBUTE_UNUSED) 968 { 969 disassemble_info *info = (disassemble_info *) dis_info; 970 const CGEN_KEYWORD_ENTRY *ke; 971 972 ke = cgen_keyword_lookup_value (keyword_table, value); 973 if (ke != NULL) 974 (*info->fprintf_func) (info->stream, "%s", ke->name); 975 else 976 (*info->fprintf_func) (info->stream, "???"); 977 } 978 979 /* Default insn printer. 981 982 DIS_INFO is defined as `void *' so the disassembler needn't know anything 983 about disassemble_info. */ 984 985 static void 986 print_insn_normal (CGEN_CPU_DESC cd, 987 void *dis_info, 988 const CGEN_INSN *insn, 989 CGEN_FIELDS *fields, 990 bfd_vma pc, 991 int length) 992 { 993 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 994 disassemble_info *info = (disassemble_info *) dis_info; 995 const CGEN_SYNTAX_CHAR_TYPE *syn; 996 997 CGEN_INIT_PRINT (cd); 998 999 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 1000 { 1001 if (CGEN_SYNTAX_MNEMONIC_P (*syn)) 1002 { 1003 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); 1004 continue; 1005 } 1006 if (CGEN_SYNTAX_CHAR_P (*syn)) 1007 { 1008 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); 1009 continue; 1010 } 1011 1012 /* We have an operand. */ 1013 m32c_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, 1014 fields, CGEN_INSN_ATTRS (insn), pc, length); 1015 } 1016 } 1017 1018 /* Subroutine of print_insn. Reads an insn into the given buffers and updates 1020 the extract info. 1021 Returns 0 if all is well, non-zero otherwise. */ 1022 1023 static int 1024 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 1025 bfd_vma pc, 1026 disassemble_info *info, 1027 bfd_byte *buf, 1028 int buflen, 1029 CGEN_EXTRACT_INFO *ex_info, 1030 unsigned long *insn_value) 1031 { 1032 int status = (*info->read_memory_func) (pc, buf, buflen, info); 1033 1034 if (status != 0) 1035 { 1036 (*info->memory_error_func) (status, pc, info); 1037 return -1; 1038 } 1039 1040 ex_info->dis_info = info; 1041 ex_info->valid = (1 << buflen) - 1; 1042 ex_info->insn_bytes = buf; 1043 1044 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); 1045 return 0; 1046 } 1047 1048 /* Utility to print an insn. 1049 BUF is the base part of the insn, target byte order, BUFLEN bytes long. 1050 The result is the size of the insn in bytes or zero for an unknown insn 1051 or -1 if an error occurs fetching data (memory_error_func will have 1052 been called). */ 1053 1054 static int 1055 print_insn (CGEN_CPU_DESC cd, 1056 bfd_vma pc, 1057 disassemble_info *info, 1058 bfd_byte *buf, 1059 unsigned int buflen) 1060 { 1061 CGEN_INSN_INT insn_value; 1062 const CGEN_INSN_LIST *insn_list; 1063 CGEN_EXTRACT_INFO ex_info; 1064 int basesize; 1065 1066 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ 1067 basesize = cd->base_insn_bitsize < buflen * 8 ? 1068 cd->base_insn_bitsize : buflen * 8; 1069 insn_value = cgen_get_insn_value (cd, buf, basesize); 1070 1071 1072 /* Fill in ex_info fields like read_insn would. Don't actually call 1073 read_insn, since the incoming buffer is already read (and possibly 1074 modified a la m32r). */ 1075 ex_info.valid = (1 << buflen) - 1; 1076 ex_info.dis_info = info; 1077 ex_info.insn_bytes = buf; 1078 1079 /* The instructions are stored in hash lists. 1080 Pick the first one and keep trying until we find the right one. */ 1081 1082 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); 1083 while (insn_list != NULL) 1084 { 1085 const CGEN_INSN *insn = insn_list->insn; 1086 CGEN_FIELDS fields; 1087 int length; 1088 unsigned long insn_value_cropped; 1089 1090 #ifdef CGEN_VALIDATE_INSN_SUPPORTED 1091 /* Not needed as insn shouldn't be in hash lists if not supported. */ 1092 /* Supported by this cpu? */ 1093 if (! m32c_cgen_insn_supported (cd, insn)) 1094 { 1095 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 1096 continue; 1097 } 1098 #endif 1099 1100 /* Basic bit mask must be correct. */ 1101 /* ??? May wish to allow target to defer this check until the extract 1102 handler. */ 1103 1104 /* Base size may exceed this instruction's size. Extract the 1105 relevant part from the buffer. */ 1106 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && 1107 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 1108 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 1109 info->endian == BFD_ENDIAN_BIG); 1110 else 1111 insn_value_cropped = insn_value; 1112 1113 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) 1114 == CGEN_INSN_BASE_VALUE (insn)) 1115 { 1116 /* Printing is handled in two passes. The first pass parses the 1117 machine insn and extracts the fields. The second pass prints 1118 them. */ 1119 1120 /* Make sure the entire insn is loaded into insn_value, if it 1121 can fit. */ 1122 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && 1123 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 1124 { 1125 unsigned long full_insn_value; 1126 int rc = read_insn (cd, pc, info, buf, 1127 CGEN_INSN_BITSIZE (insn) / 8, 1128 & ex_info, & full_insn_value); 1129 if (rc != 0) 1130 return rc; 1131 length = CGEN_EXTRACT_FN (cd, insn) 1132 (cd, insn, &ex_info, full_insn_value, &fields, pc); 1133 } 1134 else 1135 length = CGEN_EXTRACT_FN (cd, insn) 1136 (cd, insn, &ex_info, insn_value_cropped, &fields, pc); 1137 1138 /* Length < 0 -> error. */ 1139 if (length < 0) 1140 return length; 1141 if (length > 0) 1142 { 1143 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); 1144 /* Length is in bits, result is in bytes. */ 1145 return length / 8; 1146 } 1147 } 1148 1149 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 1150 } 1151 1152 return 0; 1153 } 1154 1155 /* Default value for CGEN_PRINT_INSN. 1156 The result is the size of the insn in bytes or zero for an unknown insn 1157 or -1 if an error occured fetching bytes. */ 1158 1159 #ifndef CGEN_PRINT_INSN 1160 #define CGEN_PRINT_INSN default_print_insn 1161 #endif 1162 1163 static int 1164 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 1165 { 1166 bfd_byte buf[CGEN_MAX_INSN_SIZE]; 1167 int buflen; 1168 int status; 1169 1170 /* Attempt to read the base part of the insn. */ 1171 buflen = cd->base_insn_bitsize / 8; 1172 status = (*info->read_memory_func) (pc, buf, buflen, info); 1173 1174 /* Try again with the minimum part, if min < base. */ 1175 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) 1176 { 1177 buflen = cd->min_insn_bitsize / 8; 1178 status = (*info->read_memory_func) (pc, buf, buflen, info); 1179 } 1180 1181 if (status != 0) 1182 { 1183 (*info->memory_error_func) (status, pc, info); 1184 return -1; 1185 } 1186 1187 return print_insn (cd, pc, info, buf, buflen); 1188 } 1189 1190 /* Main entry point. 1191 Print one instruction from PC on INFO->STREAM. 1192 Return the size of the instruction (in bytes). */ 1193 1194 typedef struct cpu_desc_list 1195 { 1196 struct cpu_desc_list *next; 1197 CGEN_BITSET *isa; 1198 int mach; 1199 int endian; 1200 CGEN_CPU_DESC cd; 1201 } cpu_desc_list; 1202 1203 int 1204 print_insn_m32c (bfd_vma pc, disassemble_info *info) 1205 { 1206 static cpu_desc_list *cd_list = 0; 1207 cpu_desc_list *cl = 0; 1208 static CGEN_CPU_DESC cd = 0; 1209 static CGEN_BITSET *prev_isa; 1210 static int prev_mach; 1211 static int prev_endian; 1212 int length; 1213 CGEN_BITSET *isa; 1214 int mach; 1215 int endian = (info->endian == BFD_ENDIAN_BIG 1216 ? CGEN_ENDIAN_BIG 1217 : CGEN_ENDIAN_LITTLE); 1218 enum bfd_architecture arch; 1219 1220 /* ??? gdb will set mach but leave the architecture as "unknown" */ 1221 #ifndef CGEN_BFD_ARCH 1222 #define CGEN_BFD_ARCH bfd_arch_m32c 1223 #endif 1224 arch = info->arch; 1225 if (arch == bfd_arch_unknown) 1226 arch = CGEN_BFD_ARCH; 1227 1228 /* There's no standard way to compute the machine or isa number 1229 so we leave it to the target. */ 1230 #ifdef CGEN_COMPUTE_MACH 1231 mach = CGEN_COMPUTE_MACH (info); 1232 #else 1233 mach = info->mach; 1234 #endif 1235 1236 #ifdef CGEN_COMPUTE_ISA 1237 { 1238 static CGEN_BITSET *permanent_isa; 1239 1240 if (!permanent_isa) 1241 permanent_isa = cgen_bitset_create (MAX_ISAS); 1242 isa = permanent_isa; 1243 cgen_bitset_clear (isa); 1244 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); 1245 } 1246 #else 1247 isa = info->insn_sets; 1248 #endif 1249 1250 /* If we've switched cpu's, try to find a handle we've used before */ 1251 if (cd 1252 && (cgen_bitset_compare (isa, prev_isa) != 0 1253 || mach != prev_mach 1254 || endian != prev_endian)) 1255 { 1256 cd = 0; 1257 for (cl = cd_list; cl; cl = cl->next) 1258 { 1259 if (cgen_bitset_compare (cl->isa, isa) == 0 && 1260 cl->mach == mach && 1261 cl->endian == endian) 1262 { 1263 cd = cl->cd; 1264 prev_isa = cd->isas; 1265 break; 1266 } 1267 } 1268 } 1269 1270 /* If we haven't initialized yet, initialize the opcode table. */ 1271 if (! cd) 1272 { 1273 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); 1274 const char *mach_name; 1275 1276 if (!arch_type) 1277 abort (); 1278 mach_name = arch_type->printable_name; 1279 1280 prev_isa = cgen_bitset_copy (isa); 1281 prev_mach = mach; 1282 prev_endian = endian; 1283 cd = m32c_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, 1284 CGEN_CPU_OPEN_BFDMACH, mach_name, 1285 CGEN_CPU_OPEN_ENDIAN, prev_endian, 1286 CGEN_CPU_OPEN_END); 1287 if (!cd) 1288 abort (); 1289 1290 /* Save this away for future reference. */ 1291 cl = xmalloc (sizeof (struct cpu_desc_list)); 1292 cl->cd = cd; 1293 cl->isa = prev_isa; 1294 cl->mach = mach; 1295 cl->endian = endian; 1296 cl->next = cd_list; 1297 cd_list = cl; 1298 1299 m32c_cgen_init_dis (cd); 1300 } 1301 1302 /* We try to have as much common code as possible. 1303 But at this point some targets need to take over. */ 1304 /* ??? Some targets may need a hook elsewhere. Try to avoid this, 1305 but if not possible try to move this hook elsewhere rather than 1306 have two hooks. */ 1307 length = CGEN_PRINT_INSN (cd, pc, info); 1308 if (length > 0) 1309 return length; 1310 if (length < 0) 1311 return -1; 1312 1313 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 1314 return cd->default_insn_bitsize / 8; 1315 } 1316