1 //===-- TargetPassConfig.cpp - Target independent code generation passes --===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines interfaces to access the target independent code 11 // generation passes provided by the LLVM backend. 12 // 13 //===---------------------------------------------------------------------===// 14 15 #include "llvm/CodeGen/TargetPassConfig.h" 16 17 #include "llvm/Analysis/BasicAliasAnalysis.h" 18 #include "llvm/Analysis/CFLAndersAliasAnalysis.h" 19 #include "llvm/Analysis/CFLSteensAliasAnalysis.h" 20 #include "llvm/Analysis/CallGraphSCCPass.h" 21 #include "llvm/Analysis/Passes.h" 22 #include "llvm/Analysis/ScopedNoAliasAA.h" 23 #include "llvm/Analysis/TypeBasedAliasAnalysis.h" 24 #include "llvm/CodeGen/MachineFunctionPass.h" 25 #include "llvm/CodeGen/RegAllocRegistry.h" 26 #include "llvm/CodeGen/RegisterUsageInfo.h" 27 #include "llvm/IR/IRPrintingPasses.h" 28 #include "llvm/IR/LegacyPassManager.h" 29 #include "llvm/IR/Verifier.h" 30 #include "llvm/MC/MCAsmInfo.h" 31 #include "llvm/Support/Debug.h" 32 #include "llvm/Support/ErrorHandling.h" 33 #include "llvm/Support/raw_ostream.h" 34 #include "llvm/Target/TargetMachine.h" 35 #include "llvm/Transforms/Instrumentation.h" 36 #include "llvm/Transforms/Scalar.h" 37 #include "llvm/Transforms/Utils/SymbolRewriter.h" 38 39 using namespace llvm; 40 41 static cl::opt<bool> DisablePostRA("disable-post-ra", cl::Hidden, 42 cl::desc("Disable Post Regalloc")); 43 static cl::opt<bool> DisableBranchFold("disable-branch-fold", cl::Hidden, 44 cl::desc("Disable branch folding")); 45 static cl::opt<bool> DisableTailDuplicate("disable-tail-duplicate", cl::Hidden, 46 cl::desc("Disable tail duplication")); 47 static cl::opt<bool> DisableEarlyTailDup("disable-early-taildup", cl::Hidden, 48 cl::desc("Disable pre-register allocation tail duplication")); 49 static cl::opt<bool> DisableBlockPlacement("disable-block-placement", 50 cl::Hidden, cl::desc("Disable probability-driven block placement")); 51 static cl::opt<bool> EnableBlockPlacementStats("enable-block-placement-stats", 52 cl::Hidden, cl::desc("Collect probability-driven block placement stats")); 53 static cl::opt<bool> DisableSSC("disable-ssc", cl::Hidden, 54 cl::desc("Disable Stack Slot Coloring")); 55 static cl::opt<bool> DisableMachineDCE("disable-machine-dce", cl::Hidden, 56 cl::desc("Disable Machine Dead Code Elimination")); 57 static cl::opt<bool> DisableEarlyIfConversion("disable-early-ifcvt", cl::Hidden, 58 cl::desc("Disable Early If-conversion")); 59 static cl::opt<bool> DisableMachineLICM("disable-machine-licm", cl::Hidden, 60 cl::desc("Disable Machine LICM")); 61 static cl::opt<bool> DisableMachineCSE("disable-machine-cse", cl::Hidden, 62 cl::desc("Disable Machine Common Subexpression Elimination")); 63 static cl::opt<cl::boolOrDefault> OptimizeRegAlloc( 64 "optimize-regalloc", cl::Hidden, 65 cl::desc("Enable optimized register allocation compilation path.")); 66 static cl::opt<bool> DisablePostRAMachineLICM("disable-postra-machine-licm", 67 cl::Hidden, 68 cl::desc("Disable Machine LICM")); 69 static cl::opt<bool> DisableMachineSink("disable-machine-sink", cl::Hidden, 70 cl::desc("Disable Machine Sinking")); 71 static cl::opt<bool> DisableLSR("disable-lsr", cl::Hidden, 72 cl::desc("Disable Loop Strength Reduction Pass")); 73 static cl::opt<bool> DisableConstantHoisting("disable-constant-hoisting", 74 cl::Hidden, cl::desc("Disable ConstantHoisting")); 75 static cl::opt<bool> DisableCGP("disable-cgp", cl::Hidden, 76 cl::desc("Disable Codegen Prepare")); 77 static cl::opt<bool> DisableCopyProp("disable-copyprop", cl::Hidden, 78 cl::desc("Disable Copy Propagation pass")); 79 static cl::opt<bool> DisablePartialLibcallInlining("disable-partial-libcall-inlining", 80 cl::Hidden, cl::desc("Disable Partial Libcall Inlining")); 81 static cl::opt<bool> EnableImplicitNullChecks( 82 "enable-implicit-null-checks", 83 cl::desc("Fold null checks into faulting memory operations"), 84 cl::init(false)); 85 static cl::opt<bool> PrintLSR("print-lsr-output", cl::Hidden, 86 cl::desc("Print LLVM IR produced by the loop-reduce pass")); 87 static cl::opt<bool> PrintISelInput("print-isel-input", cl::Hidden, 88 cl::desc("Print LLVM IR input to isel pass")); 89 static cl::opt<bool> PrintGCInfo("print-gc", cl::Hidden, 90 cl::desc("Dump garbage collector data")); 91 static cl::opt<bool> VerifyMachineCode("verify-machineinstrs", cl::Hidden, 92 cl::desc("Verify generated machine code"), 93 cl::init(false), 94 cl::ZeroOrMore); 95 96 static cl::opt<std::string> 97 PrintMachineInstrs("print-machineinstrs", cl::ValueOptional, 98 cl::desc("Print machine instrs"), 99 cl::value_desc("pass-name"), cl::init("option-unspecified")); 100 101 // Temporary option to allow experimenting with MachineScheduler as a post-RA 102 // scheduler. Targets can "properly" enable this with 103 // substitutePass(&PostRASchedulerID, &PostMachineSchedulerID). 104 // Targets can return true in targetSchedulesPostRAScheduling() and 105 // insert a PostRA scheduling pass wherever it wants. 106 cl::opt<bool> MISchedPostRA("misched-postra", cl::Hidden, 107 cl::desc("Run MachineScheduler post regalloc (independent of preRA sched)")); 108 109 // Experimental option to run live interval analysis early. 110 static cl::opt<bool> EarlyLiveIntervals("early-live-intervals", cl::Hidden, 111 cl::desc("Run live interval analysis earlier in the pipeline")); 112 113 // Experimental option to use CFL-AA in codegen 114 enum class CFLAAType { None, Steensgaard, Andersen, Both }; 115 static cl::opt<CFLAAType> UseCFLAA( 116 "use-cfl-aa-in-codegen", cl::init(CFLAAType::None), cl::Hidden, 117 cl::desc("Enable the new, experimental CFL alias analysis in CodeGen"), 118 cl::values(clEnumValN(CFLAAType::None, "none", "Disable CFL-AA"), 119 clEnumValN(CFLAAType::Steensgaard, "steens", 120 "Enable unification-based CFL-AA"), 121 clEnumValN(CFLAAType::Andersen, "anders", 122 "Enable inclusion-based CFL-AA"), 123 clEnumValN(CFLAAType::Both, "both", 124 "Enable both variants of CFL-AA"), 125 clEnumValEnd)); 126 127 /// Allow standard passes to be disabled by command line options. This supports 128 /// simple binary flags that either suppress the pass or do nothing. 129 /// i.e. -disable-mypass=false has no effect. 130 /// These should be converted to boolOrDefault in order to use applyOverride. 131 static IdentifyingPassPtr applyDisable(IdentifyingPassPtr PassID, 132 bool Override) { 133 if (Override) 134 return IdentifyingPassPtr(); 135 return PassID; 136 } 137 138 /// Allow standard passes to be disabled by the command line, regardless of who 139 /// is adding the pass. 140 /// 141 /// StandardID is the pass identified in the standard pass pipeline and provided 142 /// to addPass(). It may be a target-specific ID in the case that the target 143 /// directly adds its own pass, but in that case we harmlessly fall through. 144 /// 145 /// TargetID is the pass that the target has configured to override StandardID. 146 /// 147 /// StandardID may be a pseudo ID. In that case TargetID is the name of the real 148 /// pass to run. This allows multiple options to control a single pass depending 149 /// on where in the pipeline that pass is added. 150 static IdentifyingPassPtr overridePass(AnalysisID StandardID, 151 IdentifyingPassPtr TargetID) { 152 if (StandardID == &PostRASchedulerID) 153 return applyDisable(TargetID, DisablePostRA); 154 155 if (StandardID == &BranchFolderPassID) 156 return applyDisable(TargetID, DisableBranchFold); 157 158 if (StandardID == &TailDuplicateID) 159 return applyDisable(TargetID, DisableTailDuplicate); 160 161 if (StandardID == &TargetPassConfig::EarlyTailDuplicateID) 162 return applyDisable(TargetID, DisableEarlyTailDup); 163 164 if (StandardID == &MachineBlockPlacementID) 165 return applyDisable(TargetID, DisableBlockPlacement); 166 167 if (StandardID == &StackSlotColoringID) 168 return applyDisable(TargetID, DisableSSC); 169 170 if (StandardID == &DeadMachineInstructionElimID) 171 return applyDisable(TargetID, DisableMachineDCE); 172 173 if (StandardID == &EarlyIfConverterID) 174 return applyDisable(TargetID, DisableEarlyIfConversion); 175 176 if (StandardID == &MachineLICMID) 177 return applyDisable(TargetID, DisableMachineLICM); 178 179 if (StandardID == &MachineCSEID) 180 return applyDisable(TargetID, DisableMachineCSE); 181 182 if (StandardID == &TargetPassConfig::PostRAMachineLICMID) 183 return applyDisable(TargetID, DisablePostRAMachineLICM); 184 185 if (StandardID == &MachineSinkingID) 186 return applyDisable(TargetID, DisableMachineSink); 187 188 if (StandardID == &MachineCopyPropagationID) 189 return applyDisable(TargetID, DisableCopyProp); 190 191 return TargetID; 192 } 193 194 //===---------------------------------------------------------------------===// 195 /// TargetPassConfig 196 //===---------------------------------------------------------------------===// 197 198 INITIALIZE_PASS(TargetPassConfig, "targetpassconfig", 199 "Target Pass Configuration", false, false) 200 char TargetPassConfig::ID = 0; 201 202 // Pseudo Pass IDs. 203 char TargetPassConfig::EarlyTailDuplicateID = 0; 204 char TargetPassConfig::PostRAMachineLICMID = 0; 205 206 namespace { 207 struct InsertedPass { 208 AnalysisID TargetPassID; 209 IdentifyingPassPtr InsertedPassID; 210 bool VerifyAfter; 211 bool PrintAfter; 212 213 InsertedPass(AnalysisID TargetPassID, IdentifyingPassPtr InsertedPassID, 214 bool VerifyAfter, bool PrintAfter) 215 : TargetPassID(TargetPassID), InsertedPassID(InsertedPassID), 216 VerifyAfter(VerifyAfter), PrintAfter(PrintAfter) {} 217 218 Pass *getInsertedPass() const { 219 assert(InsertedPassID.isValid() && "Illegal Pass ID!"); 220 if (InsertedPassID.isInstance()) 221 return InsertedPassID.getInstance(); 222 Pass *NP = Pass::createPass(InsertedPassID.getID()); 223 assert(NP && "Pass ID not registered"); 224 return NP; 225 } 226 }; 227 } 228 229 namespace llvm { 230 class PassConfigImpl { 231 public: 232 // List of passes explicitly substituted by this target. Normally this is 233 // empty, but it is a convenient way to suppress or replace specific passes 234 // that are part of a standard pass pipeline without overridding the entire 235 // pipeline. This mechanism allows target options to inherit a standard pass's 236 // user interface. For example, a target may disable a standard pass by 237 // default by substituting a pass ID of zero, and the user may still enable 238 // that standard pass with an explicit command line option. 239 DenseMap<AnalysisID,IdentifyingPassPtr> TargetPasses; 240 241 /// Store the pairs of <AnalysisID, AnalysisID> of which the second pass 242 /// is inserted after each instance of the first one. 243 SmallVector<InsertedPass, 4> InsertedPasses; 244 }; 245 } // namespace llvm 246 247 // Out of line virtual method. 248 TargetPassConfig::~TargetPassConfig() { 249 delete Impl; 250 } 251 252 // Out of line constructor provides default values for pass options and 253 // registers all common codegen passes. 254 TargetPassConfig::TargetPassConfig(TargetMachine *tm, PassManagerBase &pm) 255 : ImmutablePass(ID), PM(&pm), StartBefore(nullptr), StartAfter(nullptr), 256 StopAfter(nullptr), Started(true), Stopped(false), 257 AddingMachinePasses(false), TM(tm), Impl(nullptr), Initialized(false), 258 DisableVerify(false), EnableTailMerge(true) { 259 260 Impl = new PassConfigImpl(); 261 262 // Register all target independent codegen passes to activate their PassIDs, 263 // including this pass itself. 264 initializeCodeGen(*PassRegistry::getPassRegistry()); 265 266 // Also register alias analysis passes required by codegen passes. 267 initializeBasicAAWrapperPassPass(*PassRegistry::getPassRegistry()); 268 initializeAAResultsWrapperPassPass(*PassRegistry::getPassRegistry()); 269 270 // Substitute Pseudo Pass IDs for real ones. 271 substitutePass(&EarlyTailDuplicateID, &TailDuplicateID); 272 substitutePass(&PostRAMachineLICMID, &MachineLICMID); 273 274 if (StringRef(PrintMachineInstrs.getValue()).equals("")) 275 TM->Options.PrintMachineCode = true; 276 } 277 278 CodeGenOpt::Level TargetPassConfig::getOptLevel() const { 279 return TM->getOptLevel(); 280 } 281 282 /// Insert InsertedPassID pass after TargetPassID. 283 void TargetPassConfig::insertPass(AnalysisID TargetPassID, 284 IdentifyingPassPtr InsertedPassID, 285 bool VerifyAfter, bool PrintAfter) { 286 assert(((!InsertedPassID.isInstance() && 287 TargetPassID != InsertedPassID.getID()) || 288 (InsertedPassID.isInstance() && 289 TargetPassID != InsertedPassID.getInstance()->getPassID())) && 290 "Insert a pass after itself!"); 291 Impl->InsertedPasses.emplace_back(TargetPassID, InsertedPassID, VerifyAfter, 292 PrintAfter); 293 } 294 295 /// createPassConfig - Create a pass configuration object to be used by 296 /// addPassToEmitX methods for generating a pipeline of CodeGen passes. 297 /// 298 /// Targets may override this to extend TargetPassConfig. 299 TargetPassConfig *LLVMTargetMachine::createPassConfig(PassManagerBase &PM) { 300 return new TargetPassConfig(this, PM); 301 } 302 303 TargetPassConfig::TargetPassConfig() 304 : ImmutablePass(ID), PM(nullptr) { 305 llvm_unreachable("TargetPassConfig should not be constructed on-the-fly"); 306 } 307 308 // Helper to verify the analysis is really immutable. 309 void TargetPassConfig::setOpt(bool &Opt, bool Val) { 310 assert(!Initialized && "PassConfig is immutable"); 311 Opt = Val; 312 } 313 314 void TargetPassConfig::substitutePass(AnalysisID StandardID, 315 IdentifyingPassPtr TargetID) { 316 Impl->TargetPasses[StandardID] = TargetID; 317 } 318 319 IdentifyingPassPtr TargetPassConfig::getPassSubstitution(AnalysisID ID) const { 320 DenseMap<AnalysisID, IdentifyingPassPtr>::const_iterator 321 I = Impl->TargetPasses.find(ID); 322 if (I == Impl->TargetPasses.end()) 323 return ID; 324 return I->second; 325 } 326 327 bool TargetPassConfig::isPassSubstitutedOrOverridden(AnalysisID ID) const { 328 IdentifyingPassPtr TargetID = getPassSubstitution(ID); 329 IdentifyingPassPtr FinalPtr = overridePass(ID, TargetID); 330 return !FinalPtr.isValid() || FinalPtr.isInstance() || 331 FinalPtr.getID() != ID; 332 } 333 334 /// Add a pass to the PassManager if that pass is supposed to be run. If the 335 /// Started/Stopped flags indicate either that the compilation should start at 336 /// a later pass or that it should stop after an earlier pass, then do not add 337 /// the pass. Finally, compare the current pass against the StartAfter 338 /// and StopAfter options and change the Started/Stopped flags accordingly. 339 void TargetPassConfig::addPass(Pass *P, bool verifyAfter, bool printAfter) { 340 assert(!Initialized && "PassConfig is immutable"); 341 342 // Cache the Pass ID here in case the pass manager finds this pass is 343 // redundant with ones already scheduled / available, and deletes it. 344 // Fundamentally, once we add the pass to the manager, we no longer own it 345 // and shouldn't reference it. 346 AnalysisID PassID = P->getPassID(); 347 348 if (StartBefore == PassID) 349 Started = true; 350 if (Started && !Stopped) { 351 std::string Banner; 352 // Construct banner message before PM->add() as that may delete the pass. 353 if (AddingMachinePasses && (printAfter || verifyAfter)) 354 Banner = std::string("After ") + std::string(P->getPassName()); 355 PM->add(P); 356 if (AddingMachinePasses) { 357 if (printAfter) 358 addPrintPass(Banner); 359 if (verifyAfter) 360 addVerifyPass(Banner); 361 } 362 363 // Add the passes after the pass P if there is any. 364 for (auto IP : Impl->InsertedPasses) { 365 if (IP.TargetPassID == PassID) 366 addPass(IP.getInsertedPass(), IP.VerifyAfter, IP.PrintAfter); 367 } 368 } else { 369 delete P; 370 } 371 if (StopAfter == PassID) 372 Stopped = true; 373 if (StartAfter == PassID) 374 Started = true; 375 if (Stopped && !Started) 376 report_fatal_error("Cannot stop compilation after pass that is not run"); 377 } 378 379 /// Add a CodeGen pass at this point in the pipeline after checking for target 380 /// and command line overrides. 381 /// 382 /// addPass cannot return a pointer to the pass instance because is internal the 383 /// PassManager and the instance we create here may already be freed. 384 AnalysisID TargetPassConfig::addPass(AnalysisID PassID, bool verifyAfter, 385 bool printAfter) { 386 IdentifyingPassPtr TargetID = getPassSubstitution(PassID); 387 IdentifyingPassPtr FinalPtr = overridePass(PassID, TargetID); 388 if (!FinalPtr.isValid()) 389 return nullptr; 390 391 Pass *P; 392 if (FinalPtr.isInstance()) 393 P = FinalPtr.getInstance(); 394 else { 395 P = Pass::createPass(FinalPtr.getID()); 396 if (!P) 397 llvm_unreachable("Pass ID not registered"); 398 } 399 AnalysisID FinalID = P->getPassID(); 400 addPass(P, verifyAfter, printAfter); // Ends the lifetime of P. 401 402 return FinalID; 403 } 404 405 void TargetPassConfig::printAndVerify(const std::string &Banner) { 406 addPrintPass(Banner); 407 addVerifyPass(Banner); 408 } 409 410 void TargetPassConfig::addPrintPass(const std::string &Banner) { 411 if (TM->shouldPrintMachineCode()) 412 PM->add(createMachineFunctionPrinterPass(dbgs(), Banner)); 413 } 414 415 void TargetPassConfig::addVerifyPass(const std::string &Banner) { 416 if (VerifyMachineCode) 417 PM->add(createMachineVerifierPass(Banner)); 418 } 419 420 /// Add common target configurable passes that perform LLVM IR to IR transforms 421 /// following machine independent optimization. 422 void TargetPassConfig::addIRPasses() { 423 switch (UseCFLAA) { 424 case CFLAAType::Steensgaard: 425 addPass(createCFLSteensAAWrapperPass()); 426 break; 427 case CFLAAType::Andersen: 428 addPass(createCFLAndersAAWrapperPass()); 429 break; 430 case CFLAAType::Both: 431 addPass(createCFLAndersAAWrapperPass()); 432 addPass(createCFLSteensAAWrapperPass()); 433 break; 434 default: 435 break; 436 } 437 438 // Basic AliasAnalysis support. 439 // Add TypeBasedAliasAnalysis before BasicAliasAnalysis so that 440 // BasicAliasAnalysis wins if they disagree. This is intended to help 441 // support "obvious" type-punning idioms. 442 addPass(createTypeBasedAAWrapperPass()); 443 addPass(createScopedNoAliasAAWrapperPass()); 444 addPass(createBasicAAWrapperPass()); 445 446 // Before running any passes, run the verifier to determine if the input 447 // coming from the front-end and/or optimizer is valid. 448 if (!DisableVerify) 449 addPass(createVerifierPass()); 450 451 // Run loop strength reduction before anything else. 452 if (getOptLevel() != CodeGenOpt::None && !DisableLSR) { 453 addPass(createLoopStrengthReducePass()); 454 if (PrintLSR) 455 addPass(createPrintFunctionPass(dbgs(), "\n\n*** Code after LSR ***\n")); 456 } 457 458 // Run GC lowering passes for builtin collectors 459 // TODO: add a pass insertion point here 460 addPass(createGCLoweringPass()); 461 addPass(createShadowStackGCLoweringPass()); 462 463 // Make sure that no unreachable blocks are instruction selected. 464 addPass(createUnreachableBlockEliminationPass()); 465 466 // Prepare expensive constants for SelectionDAG. 467 if (getOptLevel() != CodeGenOpt::None && !DisableConstantHoisting) 468 addPass(createConstantHoistingPass()); 469 470 if (getOptLevel() != CodeGenOpt::None && !DisablePartialLibcallInlining) 471 addPass(createPartiallyInlineLibCallsPass()); 472 } 473 474 /// Turn exception handling constructs into something the code generators can 475 /// handle. 476 void TargetPassConfig::addPassesToHandleExceptions() { 477 switch (TM->getMCAsmInfo()->getExceptionHandlingType()) { 478 case ExceptionHandling::SjLj: 479 // SjLj piggy-backs on dwarf for this bit. The cleanups done apply to both 480 // Dwarf EH prepare needs to be run after SjLj prepare. Otherwise, 481 // catch info can get misplaced when a selector ends up more than one block 482 // removed from the parent invoke(s). This could happen when a landing 483 // pad is shared by multiple invokes and is also a target of a normal 484 // edge from elsewhere. 485 addPass(createSjLjEHPreparePass()); 486 // FALLTHROUGH 487 case ExceptionHandling::DwarfCFI: 488 case ExceptionHandling::ARM: 489 addPass(createDwarfEHPass(TM)); 490 break; 491 case ExceptionHandling::WinEH: 492 // We support using both GCC-style and MSVC-style exceptions on Windows, so 493 // add both preparation passes. Each pass will only actually run if it 494 // recognizes the personality function. 495 addPass(createWinEHPass(TM)); 496 addPass(createDwarfEHPass(TM)); 497 break; 498 case ExceptionHandling::None: 499 addPass(createLowerInvokePass()); 500 501 // The lower invoke pass may create unreachable code. Remove it. 502 addPass(createUnreachableBlockEliminationPass()); 503 break; 504 } 505 } 506 507 /// Add pass to prepare the LLVM IR for code generation. This should be done 508 /// before exception handling preparation passes. 509 void TargetPassConfig::addCodeGenPrepare() { 510 if (getOptLevel() != CodeGenOpt::None && !DisableCGP) 511 addPass(createCodeGenPreparePass(TM)); 512 addPass(createRewriteSymbolsPass()); 513 } 514 515 /// Add common passes that perform LLVM IR to IR transforms in preparation for 516 /// instruction selection. 517 void TargetPassConfig::addISelPrepare() { 518 addPreISel(); 519 520 // Force codegen to run according to the callgraph. 521 if (TM->Options.EnableIPRA) 522 addPass(new DummyCGSCCPass); 523 524 // Add both the safe stack and the stack protection passes: each of them will 525 // only protect functions that have corresponding attributes. 526 addPass(createSafeStackPass(TM)); 527 addPass(createStackProtectorPass(TM)); 528 529 if (PrintISelInput) 530 addPass(createPrintFunctionPass( 531 dbgs(), "\n\n*** Final LLVM Code input to ISel ***\n")); 532 533 // All passes which modify the LLVM IR are now complete; run the verifier 534 // to ensure that the IR is valid. 535 if (!DisableVerify) 536 addPass(createVerifierPass()); 537 } 538 539 /// Add the complete set of target-independent postISel code generator passes. 540 /// 541 /// This can be read as the standard order of major LLVM CodeGen stages. Stages 542 /// with nontrivial configuration or multiple passes are broken out below in 543 /// add%Stage routines. 544 /// 545 /// Any TargetPassConfig::addXX routine may be overriden by the Target. The 546 /// addPre/Post methods with empty header implementations allow injecting 547 /// target-specific fixups just before or after major stages. Additionally, 548 /// targets have the flexibility to change pass order within a stage by 549 /// overriding default implementation of add%Stage routines below. Each 550 /// technique has maintainability tradeoffs because alternate pass orders are 551 /// not well supported. addPre/Post works better if the target pass is easily 552 /// tied to a common pass. But if it has subtle dependencies on multiple passes, 553 /// the target should override the stage instead. 554 /// 555 /// TODO: We could use a single addPre/Post(ID) hook to allow pass injection 556 /// before/after any target-independent pass. But it's currently overkill. 557 void TargetPassConfig::addMachinePasses() { 558 AddingMachinePasses = true; 559 560 if (TM->Options.EnableIPRA) 561 addPass(createRegUsageInfoPropPass()); 562 563 // Insert a machine instr printer pass after the specified pass. 564 if (!StringRef(PrintMachineInstrs.getValue()).equals("") && 565 !StringRef(PrintMachineInstrs.getValue()).equals("option-unspecified")) { 566 const PassRegistry *PR = PassRegistry::getPassRegistry(); 567 const PassInfo *TPI = PR->getPassInfo(PrintMachineInstrs.getValue()); 568 const PassInfo *IPI = PR->getPassInfo(StringRef("machineinstr-printer")); 569 assert (TPI && IPI && "Pass ID not registered!"); 570 const char *TID = (const char *)(TPI->getTypeInfo()); 571 const char *IID = (const char *)(IPI->getTypeInfo()); 572 insertPass(TID, IID); 573 } 574 575 // Print the instruction selected machine code... 576 printAndVerify("After Instruction Selection"); 577 578 // Expand pseudo-instructions emitted by ISel. 579 addPass(&ExpandISelPseudosID); 580 581 // Add passes that optimize machine instructions in SSA form. 582 if (getOptLevel() != CodeGenOpt::None) { 583 addMachineSSAOptimization(); 584 } else { 585 // If the target requests it, assign local variables to stack slots relative 586 // to one another and simplify frame index references where possible. 587 addPass(&LocalStackSlotAllocationID, false); 588 } 589 590 // Run pre-ra passes. 591 addPreRegAlloc(); 592 593 // Run register allocation and passes that are tightly coupled with it, 594 // including phi elimination and scheduling. 595 if (getOptimizeRegAlloc()) 596 addOptimizedRegAlloc(createRegAllocPass(true)); 597 else 598 addFastRegAlloc(createRegAllocPass(false)); 599 600 // Run post-ra passes. 601 addPostRegAlloc(); 602 603 // Insert prolog/epilog code. Eliminate abstract frame index references... 604 if (getOptLevel() != CodeGenOpt::None) 605 addPass(&ShrinkWrapID); 606 607 // Prolog/Epilog inserter needs a TargetMachine to instantiate. But only 608 // do so if it hasn't been disabled, substituted, or overridden. 609 if (!isPassSubstitutedOrOverridden(&PrologEpilogCodeInserterID)) 610 addPass(createPrologEpilogInserterPass(TM)); 611 612 /// Add passes that optimize machine instructions after register allocation. 613 if (getOptLevel() != CodeGenOpt::None) 614 addMachineLateOptimization(); 615 616 // Expand pseudo instructions before second scheduling pass. 617 addPass(&ExpandPostRAPseudosID); 618 619 // Run pre-sched2 passes. 620 addPreSched2(); 621 622 if (EnableImplicitNullChecks) 623 addPass(&ImplicitNullChecksID); 624 625 // Second pass scheduler. 626 // Let Target optionally insert this pass by itself at some other 627 // point. 628 if (getOptLevel() != CodeGenOpt::None && 629 !TM->targetSchedulesPostRAScheduling()) { 630 if (MISchedPostRA) 631 addPass(&PostMachineSchedulerID); 632 else 633 addPass(&PostRASchedulerID); 634 } 635 636 // GC 637 if (addGCPasses()) { 638 if (PrintGCInfo) 639 addPass(createGCInfoPrinter(dbgs()), false, false); 640 } 641 642 // Basic block placement. 643 if (getOptLevel() != CodeGenOpt::None) 644 addBlockPlacement(); 645 646 addPreEmitPass(); 647 648 if (TM->Options.EnableIPRA) 649 // Collect register usage information and produce a register mask of 650 // clobbered registers, to be used to optimize call sites. 651 addPass(createRegUsageInfoCollector()); 652 653 addPass(&FuncletLayoutID, false); 654 655 addPass(&StackMapLivenessID, false); 656 addPass(&LiveDebugValuesID, false); 657 658 addPass(&XRayInstrumentationID, false); 659 addPass(&PatchableFunctionID, false); 660 661 AddingMachinePasses = false; 662 } 663 664 /// Add passes that optimize machine instructions in SSA form. 665 void TargetPassConfig::addMachineSSAOptimization() { 666 // Pre-ra tail duplication. 667 addPass(&EarlyTailDuplicateID); 668 669 // Optimize PHIs before DCE: removing dead PHI cycles may make more 670 // instructions dead. 671 addPass(&OptimizePHIsID, false); 672 673 // This pass merges large allocas. StackSlotColoring is a different pass 674 // which merges spill slots. 675 addPass(&StackColoringID, false); 676 677 // If the target requests it, assign local variables to stack slots relative 678 // to one another and simplify frame index references where possible. 679 addPass(&LocalStackSlotAllocationID, false); 680 681 // With optimization, dead code should already be eliminated. However 682 // there is one known exception: lowered code for arguments that are only 683 // used by tail calls, where the tail calls reuse the incoming stack 684 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll). 685 addPass(&DeadMachineInstructionElimID); 686 687 // Allow targets to insert passes that improve instruction level parallelism, 688 // like if-conversion. Such passes will typically need dominator trees and 689 // loop info, just like LICM and CSE below. 690 addILPOpts(); 691 692 addPass(&MachineLICMID, false); 693 addPass(&MachineCSEID, false); 694 addPass(&MachineSinkingID); 695 696 addPass(&PeepholeOptimizerID); 697 // Clean-up the dead code that may have been generated by peephole 698 // rewriting. 699 addPass(&DeadMachineInstructionElimID); 700 } 701 702 //===---------------------------------------------------------------------===// 703 /// Register Allocation Pass Configuration 704 //===---------------------------------------------------------------------===// 705 706 bool TargetPassConfig::getOptimizeRegAlloc() const { 707 switch (OptimizeRegAlloc) { 708 case cl::BOU_UNSET: return getOptLevel() != CodeGenOpt::None; 709 case cl::BOU_TRUE: return true; 710 case cl::BOU_FALSE: return false; 711 } 712 llvm_unreachable("Invalid optimize-regalloc state"); 713 } 714 715 /// RegisterRegAlloc's global Registry tracks allocator registration. 716 MachinePassRegistry RegisterRegAlloc::Registry; 717 718 /// A dummy default pass factory indicates whether the register allocator is 719 /// overridden on the command line. 720 LLVM_DEFINE_ONCE_FLAG(InitializeDefaultRegisterAllocatorFlag); 721 static FunctionPass *useDefaultRegisterAllocator() { return nullptr; } 722 static RegisterRegAlloc 723 defaultRegAlloc("default", 724 "pick register allocator based on -O option", 725 useDefaultRegisterAllocator); 726 727 /// -regalloc=... command line option. 728 static cl::opt<RegisterRegAlloc::FunctionPassCtor, false, 729 RegisterPassParser<RegisterRegAlloc> > 730 RegAlloc("regalloc", 731 cl::init(&useDefaultRegisterAllocator), 732 cl::desc("Register allocator to use")); 733 734 static void initializeDefaultRegisterAllocatorOnce() { 735 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault(); 736 737 if (!Ctor) { 738 Ctor = RegAlloc; 739 RegisterRegAlloc::setDefault(RegAlloc); 740 } 741 } 742 743 744 /// Instantiate the default register allocator pass for this target for either 745 /// the optimized or unoptimized allocation path. This will be added to the pass 746 /// manager by addFastRegAlloc in the unoptimized case or addOptimizedRegAlloc 747 /// in the optimized case. 748 /// 749 /// A target that uses the standard regalloc pass order for fast or optimized 750 /// allocation may still override this for per-target regalloc 751 /// selection. But -regalloc=... always takes precedence. 752 FunctionPass *TargetPassConfig::createTargetRegisterAllocator(bool Optimized) { 753 if (Optimized) 754 return createGreedyRegisterAllocator(); 755 else 756 return createFastRegisterAllocator(); 757 } 758 759 /// Find and instantiate the register allocation pass requested by this target 760 /// at the current optimization level. Different register allocators are 761 /// defined as separate passes because they may require different analysis. 762 /// 763 /// This helper ensures that the regalloc= option is always available, 764 /// even for targets that override the default allocator. 765 /// 766 /// FIXME: When MachinePassRegistry register pass IDs instead of function ptrs, 767 /// this can be folded into addPass. 768 FunctionPass *TargetPassConfig::createRegAllocPass(bool Optimized) { 769 // Initialize the global default. 770 llvm::call_once(InitializeDefaultRegisterAllocatorFlag, 771 initializeDefaultRegisterAllocatorOnce); 772 773 RegisterRegAlloc::FunctionPassCtor Ctor = RegisterRegAlloc::getDefault(); 774 if (Ctor != useDefaultRegisterAllocator) 775 return Ctor(); 776 777 // With no -regalloc= override, ask the target for a regalloc pass. 778 return createTargetRegisterAllocator(Optimized); 779 } 780 781 /// Return true if the default global register allocator is in use and 782 /// has not be overriden on the command line with '-regalloc=...' 783 bool TargetPassConfig::usingDefaultRegAlloc() const { 784 return RegAlloc.getNumOccurrences() == 0; 785 } 786 787 /// Add the minimum set of target-independent passes that are required for 788 /// register allocation. No coalescing or scheduling. 789 void TargetPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) { 790 addPass(&PHIEliminationID, false); 791 addPass(&TwoAddressInstructionPassID, false); 792 793 if (RegAllocPass) 794 addPass(RegAllocPass); 795 } 796 797 /// Add standard target-independent passes that are tightly coupled with 798 /// optimized register allocation, including coalescing, machine instruction 799 /// scheduling, and register allocation itself. 800 void TargetPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) { 801 addPass(&DetectDeadLanesID, false); 802 803 addPass(&ProcessImplicitDefsID, false); 804 805 // LiveVariables currently requires pure SSA form. 806 // 807 // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, 808 // LiveVariables can be removed completely, and LiveIntervals can be directly 809 // computed. (We still either need to regenerate kill flags after regalloc, or 810 // preferably fix the scavenger to not depend on them). 811 addPass(&LiveVariablesID, false); 812 813 // Edge splitting is smarter with machine loop info. 814 addPass(&MachineLoopInfoID, false); 815 addPass(&PHIEliminationID, false); 816 817 // Eventually, we want to run LiveIntervals before PHI elimination. 818 if (EarlyLiveIntervals) 819 addPass(&LiveIntervalsID, false); 820 821 addPass(&TwoAddressInstructionPassID, false); 822 addPass(&RegisterCoalescerID); 823 824 // The machine scheduler may accidentally create disconnected components 825 // when moving subregister definitions around, avoid this by splitting them to 826 // separate vregs before. Splitting can also improve reg. allocation quality. 827 addPass(&RenameIndependentSubregsID); 828 829 // PreRA instruction scheduling. 830 addPass(&MachineSchedulerID); 831 832 if (RegAllocPass) { 833 // Add the selected register allocation pass. 834 addPass(RegAllocPass); 835 836 // Allow targets to change the register assignments before rewriting. 837 addPreRewrite(); 838 839 // Finally rewrite virtual registers. 840 addPass(&VirtRegRewriterID); 841 842 // Perform stack slot coloring and post-ra machine LICM. 843 // 844 // FIXME: Re-enable coloring with register when it's capable of adding 845 // kill markers. 846 addPass(&StackSlotColoringID); 847 848 // Run post-ra machine LICM to hoist reloads / remats. 849 // 850 // FIXME: can this move into MachineLateOptimization? 851 addPass(&PostRAMachineLICMID); 852 } 853 } 854 855 //===---------------------------------------------------------------------===// 856 /// Post RegAlloc Pass Configuration 857 //===---------------------------------------------------------------------===// 858 859 /// Add passes that optimize machine instructions after register allocation. 860 void TargetPassConfig::addMachineLateOptimization() { 861 // Branch folding must be run after regalloc and prolog/epilog insertion. 862 addPass(&BranchFolderPassID); 863 864 // Tail duplication. 865 // Note that duplicating tail just increases code size and degrades 866 // performance for targets that require Structured Control Flow. 867 // In addition it can also make CFG irreducible. Thus we disable it. 868 if (!TM->requiresStructuredCFG()) 869 addPass(&TailDuplicateID); 870 871 // Copy propagation. 872 addPass(&MachineCopyPropagationID); 873 } 874 875 /// Add standard GC passes. 876 bool TargetPassConfig::addGCPasses() { 877 addPass(&GCMachineCodeAnalysisID, false); 878 return true; 879 } 880 881 /// Add standard basic block placement passes. 882 void TargetPassConfig::addBlockPlacement() { 883 if (addPass(&MachineBlockPlacementID)) { 884 // Run a separate pass to collect block placement statistics. 885 if (EnableBlockPlacementStats) 886 addPass(&MachineBlockPlacementStatsID); 887 } 888 } 889