| /external/llvm/include/llvm/MC/ |
| MCInstrAnalysis.h | 34 virtual bool isBranch(const MCInst &Inst) const {
35 return Info->get(Inst.getOpcode()).isBranch();
38 virtual bool isConditionalBranch(const MCInst &Inst) const {
39 return Info->get(Inst.getOpcode()).isConditionalBranch();
42 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
43 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
46 virtual bool isIndirectBranch(const MCInst &Inst) const {
47 return Info->get(Inst.getOpcode()).isIndirectBranch();
50 virtual bool isCall(const MCInst &Inst) const {
51 return Info->get(Inst.getOpcode()).isCall()
[all...] |
| MCInstBuilder.h | 23 MCInst Inst;
28 Inst.setOpcode(Opcode);
33 Inst.addOperand(MCOperand::createReg(Reg));
39 Inst.addOperand(MCOperand::createImm(Val));
45 Inst.addOperand(MCOperand::createFPImm(Val));
51 Inst.addOperand(MCOperand::createExpr(Val));
57 Inst.addOperand(MCOperand::createInst(Val));
63 Inst.addOperand(Op);
68 return Inst;
|
| /external/swiftshader/third_party/LLVM/include/llvm/MC/ |
| MCInstrAnalysis.h | 31 virtual bool isBranch(const MCInst &Inst) const {
32 return Info->get(Inst.getOpcode()).isBranch();
35 virtual bool isConditionalBranch(const MCInst &Inst) const {
36 return Info->get(Inst.getOpcode()).isBranch();
39 virtual bool isUnconditionalBranch(const MCInst &Inst) const {
40 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
43 virtual bool isIndirectBranch(const MCInst &Inst) const {
44 return Info->get(Inst.getOpcode()).isIndirectBranch();
47 virtual bool isCall(const MCInst &Inst) const {
48 return Info->get(Inst.getOpcode()).isCall()
[all...] |
| /external/llvm/lib/MC/ |
| MCInstrAnalysis.cpp | 13 bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
15 if (Inst.getNumOperands() == 0 ||
16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
19 int64_t Imm = Inst.getOperand(0).getImm();
|
| /external/swiftshader/third_party/LLVM/lib/MC/ |
| MCInstrAnalysis.cpp | 13 uint64_t MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
15 if (Inst.getNumOperands() == 0 ||
16 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
19 int64_t Imm = Inst.getOperand(0).getImm();
|
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 76 static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst,
81 static DecodeStatus DecodeRRegsRegisterClass(MCInst &Inst,
86 static DecodeStatus DecodeBitpOperand(MCInst &Inst, unsigned Val,
89 static DecodeStatus DecodeNegImmOperand(MCInst &Inst, unsigned Val,
92 static DecodeStatus Decode2RInstruction(MCInst &Inst,
97 static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
102 static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
107 static DecodeStatus Decode2RSrcDstInstruction(MCInst &Inst,
112 static DecodeStatus DecodeRUSInstruction(MCInst &Inst,
117 static DecodeStatus DecodeRUSBitpInstruction(MCInst &Inst,
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AddressTypePromotion.cpp | 108 /// - Inst is used only once (no need to insert truncate).
109 /// - Inst has only one operand that will require a sext operation (we do
111 bool shouldGetThrough(const Instruction *Inst);
119 bool canGetThrough(const Instruction *Inst);
156 bool AArch64AddressTypePromotion::canGetThrough(const Instruction *Inst) {
157 if (isa<SExtInst>(Inst))
160 const BinaryOperator *BinOp = dyn_cast<BinaryOperator>(Inst);
166 if (isa<TruncInst>(Inst) && isa<SExtInst>(Inst->getOperand(0))) {
167 const Instruction *Opnd = cast<Instruction>(Inst->getOperand(0))
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Transforms/Scalar/ |
| EarlyCSE.cpp | 47 Instruction *Inst;
49 SimpleValue(Instruction *I) : Inst(I) {
50 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!");
54 return Inst == DenseMapInfo<Instruction*>::getEmptyKey() ||
55 Inst == DenseMapInfo<Instruction*>::getTombstoneKey();
58 static bool canHandle(Instruction *Inst) {
60 if (CallInst *CI = dyn_cast<CallInst>(Inst))
62 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) ||
63 isa<GetElementPtrInst>(Inst) || isa<CmpInst>(Inst) |
[all...] |
| Sink.cpp | 56 bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB) const;
71 bool Sinking::AllUsesDominatedByBlock(Instruction *Inst,
77 for (Value::use_iterator I = Inst->use_begin(),
78 E = Inst->use_end(); I != E; ++I) {
134 Instruction *Inst = I; // The instruction to sink.
142 if (isa<DbgInfoIntrinsic>(Inst))
145 if (SinkInstruction(Inst, Stores))
154 static bool isSafeToMove(Instruction *Inst, AliasAnalysis *AA,
157 if (Inst->mayWriteToMemory()) {
158 Stores.insert(Inst);
[all...] |
| /external/llvm/lib/Analysis/ |
| CFLGraph.h | 225 void visitReturnInst(ReturnInst &Inst) {
226 if (auto RetVal = Inst.getReturnValue()) {
234 void visitPtrToIntInst(PtrToIntInst &Inst) {
235 auto *Ptr = Inst.getOperand(0);
239 void visitIntToPtrInst(IntToPtrInst &Inst) {
240 auto *Ptr = &Inst;
244 void visitCastInst(CastInst &Inst) {
245 auto *Src = Inst.getOperand(0);
246 addAssignEdge(Src, &Inst);
249 void visitBinaryOperator(BinaryOperator &Inst) {
[all...] |
| OrderedBasicBlock.cpp | 37 const Instruction *Inst = nullptr;
49 Inst = cast<Instruction>(II);
50 NumberedInsts[Inst] = NextInstPos++;
51 if (Inst == A || Inst == B)
56 assert((Inst == A || Inst == B) && "Should find A or B");
58 return Inst == A;
|
| /prebuilts/go/darwin-x86/test/interface/ |
| pointer.go | 12 type Inst interface {
13 Next() *Inst
17 code []Inst
18 start Inst
22 foo *Inst
25 func (start *Start) Next() *Inst { return nil }
28 func AddInst(Inst) *Inst {
35 var x Inst = AddInst(new(Start)) // ERROR "pointer to interface"
37 var y *Inst = new(Start) // ERROR "pointer to interface|incompatible type
[all...] |
| /prebuilts/go/linux-x86/test/interface/ |
| pointer.go | 12 type Inst interface {
13 Next() *Inst
17 code []Inst
18 start Inst
22 foo *Inst
25 func (start *Start) Next() *Inst { return nil }
28 func AddInst(Inst) *Inst {
35 var x Inst = AddInst(new(Start)) // ERROR "pointer to interface"
37 var y *Inst = new(Start) // ERROR "pointer to interface|incompatible type
[all...] |
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 77 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
83 Inst.addOperand(MCOperand::createReg(RegNo));
87 static DecodeStatus DecodeGR32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
90 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR32Regs, 16);
93 static DecodeStatus DecodeGRH32BitRegisterClass(MCInst &Inst, uint64_t RegNo,
96 return decodeRegisterClass(Inst, RegNo, SystemZMC::GRH32Regs, 16);
99 static DecodeStatus DecodeGR64BitRegisterClass(MCInst &Inst, uint64_t RegNo,
102 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR64Regs, 16);
105 static DecodeStatus DecodeGR128BitRegisterClass(MCInst &Inst, uint64_t RegNo,
108 return decodeRegisterClass(Inst, RegNo, SystemZMC::GR128Regs, 16)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/MC/MCDisassembler/ |
| EDOperand.cpp | 24 const EDInst &inst,
28 Inst(inst),
35 uint8_t operandType = inst.ThisInstInfo->operandTypes[opIndex];
59 uint8_t operandType = inst.ThisInstInfo->operandTypes[opIndex];
127 uint8_t operandType = Inst.ThisInstInfo->operandTypes[OpIndex];
138 result = Inst.Inst->getOperand(MCOpIndex).getImm();
142 unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg()
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Sink.cpp | 37 static bool AllUsesDominatedByBlock(Instruction *Inst, BasicBlock *BB,
43 for (Use &U : Inst->uses()) {
60 static bool isSafeToMove(Instruction *Inst, AliasAnalysis &AA,
63 if (Inst->mayWriteToMemory()) {
64 Stores.insert(Inst);
68 if (LoadInst *L = dyn_cast<LoadInst>(Inst)) {
75 if (isa<TerminatorInst>(Inst) || isa<PHINode>(Inst) || Inst->isEHPad() ||
76 Inst->mayThrow()
[all...] |
| EarlyCSE.cpp | 55 Instruction *Inst;
57 SimpleValue(Instruction *I) : Inst(I) {
58 assert((isSentinel() || canHandle(I)) && "Inst can't be handled!");
62 return Inst == DenseMapInfo<Instruction *>::getEmptyKey() ||
63 Inst == DenseMapInfo<Instruction *>::getTombstoneKey();
66 static bool canHandle(Instruction *Inst) {
68 if (CallInst *CI = dyn_cast<CallInst>(Inst))
70 return isa<CastInst>(Inst) || isa<BinaryOperator>(Inst) ||
71 isa<GetElementPtrInst>(Inst) || isa<CmpInst>(Inst) |
[all...] |
| /external/llvm/lib/CodeGen/GlobalISel/ |
| IRTranslator.cpp | 64 bool IRTranslator::translateBinaryOp(unsigned Opcode, const Instruction &Inst) {
69 unsigned Op0 = getOrCreateVReg(*Inst.getOperand(0));
70 unsigned Op1 = getOrCreateVReg(*Inst.getOperand(1));
71 unsigned Res = getOrCreateVReg(Inst);
72 MIRBuilder.buildInstr(Opcode, Inst.getType(), Res, Op0, Op1);
76 bool IRTranslator::translateReturn(const Instruction &Inst) {
77 assert(isa<ReturnInst>(Inst) && "Return expected");
78 const Value *Ret = cast<ReturnInst>(Inst).getReturnValue();
85 bool IRTranslator::translateBr(const Instruction &Inst) {
86 assert(isa<BranchInst>(Inst) && "Branch expected")
[all...] |
| /external/swiftshader/third_party/LLVM/tools/llvm-objdump/ |
| MCFunction.cpp | 55 MCInst Inst;
56 if (DisAsm->getInstruction(Inst, Size, Region, Index, DebugOut, nulls())){
57 Instructions.push_back(MCDecodedInst(Index, Size, Inst));
58 if (Ana->isBranch(Inst)) {
59 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size);
72 } else if (Ana->isReturn(Inst)) {
76 } else if (Ana->isCall(Inst)) {
77 uint64_t targ = Ana->evaluateBranch(Inst, Index, Size);
116 const MCDecodedInst &Inst = BB.getInsts().back();
118 if (Ana->isBranch(Inst.Inst))
[all...] |
| /external/llvm/lib/Target/Mips/Disassembler/ |
| MipsDisassembler.cpp | 71 static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
76 static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
81 static DecodeStatus DecodeGPRMM16RegisterClass(MCInst &Inst,
86 static DecodeStatus DecodeGPRMM16ZeroRegisterClass(MCInst &Inst,
91 static DecodeStatus DecodeGPRMM16MovePRegisterClass(MCInst &Inst,
96 static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
101 static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
106 static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
111 static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
116 static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
[all...] |
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiMCCodeEmitter.cpp | 52 uint64_t getBinaryCodeForInstr(const MCInst &Inst,
58 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
62 unsigned getRiMemoryOpValue(const MCInst &Inst, unsigned OpNo,
66 unsigned getRrMemoryOpValue(const MCInst &Inst, unsigned OpNo,
70 unsigned getSplsOpValue(const MCInst &Inst, unsigned OpNo,
74 unsigned getBranchTargetOpValue(const MCInst &Inst, unsigned OpNo,
78 unsigned getCallTargetOpValue(const MCInst &Inst, unsigned OpNo,
82 void encodeInstruction(const MCInst &Inst, raw_ostream &Ostream,
86 unsigned adjustPqBitsRmAndRrm(const MCInst &Inst, unsigned Value,
89 unsigned adjustPqBitsSpls(const MCInst &Inst, unsigned Value
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| InstrInfoEmitter.cpp | 52 InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
55 for (unsigned i = 0, e = Inst.Operands.size(); i != e; ++i) {
64 DagInit *MIOI = Inst.Operands[i].MIOperandInfo;
68 OperandList.push_back(Inst.Operands[i]);
70 for (unsigned j = 0, e = Inst.Operands[i].MINumOperands; j != e; ++j) {
71 OperandList.push_back(Inst.Operands[i]);
101 if (Inst.Operands[i].Rec->isSubClassOf("PredicateOperand"))
106 if (Inst.Operands[i].Rec->isSubClassOf("OptionalDefOperand"))
113 Inst.Operands[i].Constraints[j];
126 assert(!Inst.Operands[i].OperandType.empty() && "Invalid operand type.")
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 106 static DecodeStatus DecodeGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
108 static DecodeStatus DecodeGPRnopcRegisterClass(llvm::MCInst &Inst,
111 static DecodeStatus DecodetGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
113 static DecodeStatus DecodetcGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
115 static DecodeStatus DecoderGPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
117 static DecodeStatus DecodeSPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
119 static DecodeStatus DecodeDPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo,
121 static DecodeStatus DecodeDPR_8RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
123 static DecodeStatus DecodeDPR_VFP2RegisterClass(llvm::MCInst &Inst,
127 static DecodeStatus DecodeQPRRegisterClass(llvm::MCInst &Inst, unsigned RegNo
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | 141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo
[all...] |
| /external/llvm/lib/Transforms/ObjCARC/ |
| DependencyAnalysis.h | 62 Depends(DependenceKind Flavor, Instruction *Inst, const Value *Arg,
67 bool CanUse(const Instruction *Inst, const Value *Ptr, ProvenanceAnalysis &PA,
72 bool CanAlterRefCount(const Instruction *Inst, const Value *Ptr,
75 /// Returns true if we can not conservatively prove that Inst can not decrement
77 bool CanDecrementRefCount(const Instruction *Inst, const Value *Ptr,
80 static inline bool CanDecrementRefCount(const Instruction *Inst,
83 return CanDecrementRefCount(Inst, Ptr, PA, GetARCInstKind(Inst));
|
