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    Searched refs:BankSwizzle (Results 1 - 4 of 4) sorted by null

  /external/llvm/lib/Target/AMDGPU/
R600InstrInfo.h 50 enum BankSwizzle {
120 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
122 R600InstrInfo::BankSwizzle TransSwz) const;
126 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
128 R600InstrInfo::BankSwizzle TransSwz) const;
131 /// returns true and the first (in lexical order) BankSwizzle affectation
136 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
141 std::vector<BankSwizzle> &BS,
R600InstrInfo.cpp 383 R600InstrInfo::BankSwizzle Swz) {
411 getTransSwizzle(R600InstrInfo::BankSwizzle Swz, unsigned Op) {
440 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
442 R600InstrInfo::BankSwizzle TransSwz) const {
489 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
501 SwzCandidate[ResetIdx] = (R600InstrInfo::BankSwizzle)NextSwizzle;
509 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
511 R600InstrInfo::BankSwizzle TransSwz) const {
524 isConstCompatible(R600InstrInfo::BankSwizzle TransSwz,
546 std::vector<BankSwizzle> &ValidSwizzle
    [all...]
R600Packetizer.cpp 231 std::vector<R600InstrInfo::BankSwizzle> &BS,
269 // Is there a BankSwizzle set that meet Read Port limitations ?
299 std::vector<R600InstrInfo::BankSwizzle> BS;
  /external/llvm/lib/Target/AMDGPU/InstPrinter/
AMDGPUInstPrinter.cpp 712 int BankSwizzle = MI->getOperand(OpNo).getImm();
713 switch (BankSwizzle) {

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