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    Searched refs:CSSELR (Results 1 - 5 of 5) sorted by null

  /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/Common/
ArmLibPrivate.h 72 IN UINT32 CSSELR
  /device/linaro/bootloader/edk2/ArmPkg/Library/ArmLib/ArmV7/
ArmLibSupportV7.S 96 // IN UINT32 CSSELR
99 mcr p15,2,r0,c0,c0,0 @ Write Cache Size Selection Register (CSSELR)
106 // IN UINT32 CSSELR
ArmV7Support.S 226 mcr p15, 2, R10, c0, c0, 0 @ write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
ArmV7Support.asm 188 mcr p15, 2, R10, c0, c0, 0 ; write the Cache Size selection register (CSSELR) // OR in 1 for Instruction
  /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cm7.h 435 __IO uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */
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