| /external/vixl/src/aarch32/ |
| disasm-aarch32.h | 240 virtual DisassemblerStream& operator<<(DRegister reg) {
[all...] |
| assembler-aarch32.h | 350 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm);
354 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm);
357 DRegister rd,
358 DRegister rm);
370 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm);
372 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm);
375 DRegister rd
[all...] |
| macro-assembler-aarch32.h | 247 EmitLiteralCondDtDL(DataType dt, DRegister rt) : dt_(dt), rt_(rt) {}
256 DRegister rt_;
817 void Vldr(Condition cond, DataType dt, DRegister rd, RawLiteral* literal) {
824 void Vldr(DataType dt, DRegister rd, RawLiteral* literal) {
827 void Vldr(Condition cond, DRegister rd, RawLiteral* literal) {
830 void Vldr(DRegister rd, RawLiteral* literal) {
[all...] |
| disasm-aarch32.cc | [all...] |
| instructions-aarch32.cc | 85 DRegister VRegister::D() const {
87 return DRegister(GetCode());
140 DRegister VRegisterList::GetFirstAvailableDRegister() const {
142 if (((list_ >> (i * 2)) & 0x3) == 0x3) return DRegister(i);
144 return DRegister();
168 DRegister first = reglist.GetFirstDRegister();
169 DRegister last = reglist.GetLastDRegister();
178 DRegister first = nreglist.GetFirstDRegister();
201 first = DRegister(next);
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| instructions-aarch32.h | 174 class DRegister;
184 DRegister D() const;
218 class DRegister : public VRegister {
220 DRegister() : VRegister(kNoRegister, 0, kDRegSizeInBits) {}
221 explicit DRegister(uint32_t code)
244 inline std::ostream& operator<<(std::ostream& os, const DRegister reg) {
321 class DRegisterLane : public DRegister {
325 DRegisterLane(DRegister reg, uint32_t lane)
326 : DRegister(reg.GetCode()), lane_(lane) {}
327 DRegisterLane(uint32_t code, uint32_t lane) : DRegister(code), lane_(lane) {
[all...] |
| assembler-aarch32.cc | [all...] |
| /art/compiler/utils/mips/ |
| constants_mips.h | 31 enum DRegister {
52 std::ostream& operator<<(std::ostream& os, const DRegister& rhs);
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| managed_register_mips.h | 67 // [F..D[ double precision FP registers (enum DRegister)
85 // FP register (enum DRegister), or a pair of core registers (enum RegisterPair).
100 constexpr DRegister AsDRegister() const {
102 return static_cast<DRegister>(id_ - kNumberOfCoreRegIds - kNumberOfFRegIds);
107 DRegister d_reg = AsDRegister();
113 DRegister d_reg = AsDRegister();
146 // Returns true if this DRegister overlaps FRegisters.
177 static constexpr MipsManagedRegister FromDRegister(DRegister r) {
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| /art/compiler/utils/arm/ |
| assembler_thumb2.h | 203 void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
204 void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL) OVERRIDE;
206 void vmovd(DRegister dd, DRegister dm, Condition cond = AL) OVERRIDE;
210 bool vmovd(DRegister dd, double d_imm, Condition cond = AL) OVERRIDE;
214 void vldrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
215 void vstrd(DRegister dd, const Address& ad, Condition cond = AL) OVERRIDE;
218 void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) OVERRIDE
[all...] |
| assembler_arm.h | 588 virtual void vmovdrr(DRegister dm, Register rt, Register rt2, Condition cond = AL) = 0;
589 virtual void vmovrrd(Register rt, Register rt2, DRegister dm, Condition cond = AL) = 0;
591 virtual void vmovd(DRegister dd, DRegister dm, Condition cond = AL) = 0;
595 virtual bool vmovd(DRegister dd, double d_imm, Condition cond = AL) = 0;
599 virtual void vldrd(DRegister dd, const Address& ad, Condition cond = AL) = 0;
600 virtual void vstrd(DRegister dd, const Address& ad, Condition cond = AL) = 0;
603 virtual void vaddd(DRegister dd, DRegister dn, DRegister dm, Condition cond = AL) = 0
[all...] |
| constants_arm.h | 61 enum DRegister { // private marker to avoid generate-operator-out.py from processing.
98 std::ostream& operator<<(std::ostream& os, const DRegister& rhs);
396 DRegister DnField() const {
397 return static_cast<DRegister>(Bits(kRnShift, kRnBits) + (Bit(7) << 4));
399 DRegister DdField() const {
400 return static_cast<DRegister>(Bits(kRdShift, kRdBits) + (Bit(22) << 4));
402 DRegister DmField() const {
403 return static_cast<DRegister>(Bits(kRmShift, kRmBits) + (Bit(5) << 4));
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| managed_register_arm.h | 67 // [S..D[ double precision VFP registers (enum DRegister)
79 // DRegister, VFPv3-D32 only)
89 // (enum SRegister), or a VFP double precision register (enum DRegister).
114 constexpr DRegister AsDRegister() const {
116 return static_cast<DRegister>(id_ - kNumberOfCoreRegIds - kNumberOfSRegIds);
119 vixl::aarch32::DRegister AsVIXLDRegister() const {
121 return vixl::aarch32::DRegister(id_ - kNumberOfCoreRegIds - kNumberOfSRegIds);
126 DRegister d_reg = AsDRegister();
132 DRegister d_reg = AsDRegister();
183 // Returns true if this DRegister overlaps SRegisters
[all...] |
| assembler_arm_vixl.h | 140 void Vmov(vixl32::DRegister rd, double imm) {
195 void StoreDToOffset(vixl32::DRegister source, vixl32::Register base, int32_t offset);
203 void LoadDFromOffset(vixl32::DRegister reg, vixl32::Register base, int32_t offset);
|
| assembler_thumb2.cc | 438 inline int32_t Thumb2Assembler::VldrdEncoding32(DRegister dd, Register rn, int32_t offset) {
[all...] |
| assembler_arm_vixl.cc | 341 void ArmVIXLAssembler::StoreDToOffset(vixl32::DRegister source,
353 void ArmVIXLAssembler::LoadDFromOffset(vixl32::DRegister reg,
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| /art/compiler/utils/arm64/ |
| managed_register_arm64.h | 39 // [W..D[ double precision VFP registers (enum DRegister)
52 // * VFP double precision register (enum DRegister)
69 constexpr DRegister AsDRegister() const {
71 return static_cast<DRegister>(id_ - kNumberOfXRegIds - kNumberOfWRegIds);
96 constexpr DRegister AsOverlappingDRegister() const {
98 return static_cast<DRegister>(AsSRegister());
158 static constexpr Arm64ManagedRegister FromDRegister(DRegister r) {
|
| jni_macro_assembler_arm64.h | 209 void StoreDToOffset(DRegister source, XRegister base, int32_t offset);
221 void LoadDFromOffset(DRegister dest, XRegister base, int32_t offset);
|
| /art/compiler/optimizing/ |
| common_arm.h | 54 inline vixl::aarch32::DRegister HighDRegisterFrom(Location location) {
56 return vixl::aarch32::DRegister(location.AsFpuRegisterPairHigh<vixl::aarch32::DRegister>());
84 inline vixl::aarch32::DRegister DRegisterFrom(Location location) {
88 return vixl::aarch32::DRegister(reg_code / 2);
102 inline vixl::aarch32::DRegister OutputDRegister(HInstruction* instr) {
123 inline vixl::aarch32::DRegister InputDRegisterAt(HInstruction* instr, int input_index) {
158 inline vixl::aarch32::DRegister DRegisterFromS(vixl::aarch32::SRegister s) {
159 vixl::aarch32::DRegister d = vixl::aarch32::DRegister(s.GetCode() / 2)
[all...] |
| /art/runtime/arch/arm64/ |
| registers_arm64.cc | 56 std::ostream& operator<<(std::ostream& os, const DRegister& rhs) {
60 os << "DRegister[" << static_cast<int>(rhs) << "]";
|
| registers_arm64.h | 113 enum DRegister {
149 std::ostream& operator<<(std::ostream& os, const DRegister& rhs);
|
| /external/vixl/test/aarch32/ |
| test-utils-aarch32.h | 119 // DRegister accessors
177 const DRegister& dreg);
185 const DRegister& dreg);
|
| test-utils-aarch32.cc | 73 DRegister rt(i);
145 const DRegister& dreg) {
236 const DRegister& dreg) {
|
| /art/compiler/jni/quick/mips/ |
| calling_convention_mips.cc | 39 static const DRegister kJniDArgumentRegisters[] = { D6, D7 };
47 static const DRegister kManagedDArgumentRegisters[] = { D4, D5, D6, D7, D8, D9 };
|
| /art/compiler/jni/quick/arm64/ |
| calling_convention_arm64.cc | 42 static const DRegister kDArgumentRegisters[] = {
|
