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    Searched refs:DstOp (Results 1 - 5 of 5) sorted by null

  /external/llvm/lib/Target/Hexagon/
HexagonRDFOpt.cpp 105 const MachineOperand &DstOp = MI->getOperand(0);
108 assert(DstOp.getSubReg() == 0 && "Unexpected subregister");
109 mapRegs({ DstOp.getReg(), Hexagon::subreg_hireg },
111 mapRegs({ DstOp.getReg(), Hexagon::subreg_loreg },
122 const MachineOperand &DstOp = MI->getOperand(0);
124 mapRegs({ DstOp.getReg(), DstOp.getSubReg() },
  /external/llvm/lib/Target/AMDGPU/
R600ExpandSpecialInstrs.cpp 85 MachineOperand &DstOp = MI.getOperand(DstIdx);
87 DstOp.getReg(), AMDGPU::OQAP);
88 DstOp.setReg(AMDGPU::OQAP);
  /external/llvm/lib/Linker/
IRMover.cpp     [all...]
  /external/llvm/lib/Target/X86/
X86MCInstLower.cpp     [all...]
  /external/llvm/lib/CodeGen/
MachineScheduler.cpp     [all...]

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