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  /external/vixl/src/aarch64/
simulator-aarch64.cc     [all...]
simulator-aarch64.h 617 // Unsigned halve lanes of a vector, and use the saturation state to set the
634 // Signed halve lanes of a vector, and use the carry state to set the top bit.
635 LogicVRegister& Halve(VectorFormat vform) {
    [all...]

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