/external/llvm/include/llvm/Transforms/IPO/ |
DeadArgumentElimination.h | 40 RetOrArg(const Function *F, unsigned Idx, bool IsArg) 41 : F(F), Idx(Idx), IsArg(IsArg) {} 43 unsigned Idx; 48 return std::tie(F, Idx, IsArg) < std::tie(O.F, O.Idx, O.IsArg); 53 return F == O.F && Idx == O.Idx && IsArg == O.IsArg; 57 return (Twine(IsArg ? "Argument #" : "Return value #") + Twine(Idx) + 71 RetOrArg CreateRet(const Function *F, unsigned Idx) { [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXMachineFunctionInfo.h | 44 const char *getImageHandleSymbol(unsigned Idx) const { 45 assert(ImageHandleList.size() > Idx && "Bad index"); 46 return ImageHandleList[Idx].c_str();
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/external/compiler-rt/test/asan/TestCases/Linux/ |
scariness_score_test.cc | 50 void HeapBuferOverflow(int Idx, ReadOrWrite w) { 54 t[100 + Idx] = T(); 56 sink = t[100 + Idx]; 61 void HeapUseAfterFree(int Idx, ReadOrWrite w) { 67 t[Idx] = T(); 69 sink = t[Idx]; 73 void StackBufferOverflow(int Idx, ReadOrWrite w) { 76 sink = t[Idx]; 78 t[100 + Idx] = T(); 80 sink = t[100 + Idx]; [all...] |
/device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Library/Dxe/EfiDriverLib/ |
Handle.c | 68 UINTN Idx;
93 Idx = 0;
96 // Leave the Idx just beyond the matching handle.
98 for (; Idx < NumberOfHandles;) {
99 if (*Handle == HandleBuffer[Idx++]) {
108 for (; Idx < NumberOfHandles; Idx++) {
136 *Handle = HandleBuffer[Idx];
144 HandleBuffer[Idx],
156 HandleBuffer[Idx],
[all...] |
/external/llvm/lib/Target/AMDGPU/ |
AMDGPUIntrinsicInfo.cpp | 53 int Idx = Intrinsic::lookupLLVMIntrinsicByName(IntrinsicNameTable, Name); 54 if (Idx >= 0) { 55 bool IsPrefixMatch = Name.size() > strlen(IntrinsicNameTable[Idx]); 56 return IsPrefixMatch == isOverloaded(Idx + 1) 57 ? Intrinsic::num_intrinsics + Idx
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/external/clang/lib/Serialization/ |
ASTReaderStmt.cpp | 35 unsigned &Idx; 83 const ASTReader::RecordData &Record, unsigned &Idx) 84 : Reader(Reader), F(F), DeclsCursor(Cursor), Record(Record), Idx(Idx) { } 112 SourceLocation TemplateKWLoc = ReadSourceLocation(Record, Idx); 114 ArgInfo.setLAngleLoc(ReadSourceLocation(Record, Idx)); 115 ArgInfo.setRAngleLoc(ReadSourceLocation(Record, Idx)); 118 Reader.ReadTemplateArgumentLoc(F, Record, Idx)); 123 assert(Idx == NumStmtFields && "Incorrect statement field count"); 128 S->setSemiLoc(ReadSourceLocation(Record, Idx)); [all...] |
ASTReaderDecl.cpp | 45 unsigned &Idx; 92 for (unsigned I = 0, Size = Record[Idx++]; I != Size; ++I) 93 IDs.push_back(ReadDeclID(Record, Idx)); 220 const RecordData &Record, unsigned &Idx) 222 ThisDeclLoc(ThisDeclLoc), Record(Record), Idx(Idx), 463 GetTypeSourceInfo(Record, Idx); 466 DD->DeclInfo = GetTypeSourceInfo(Record, Idx); 487 if (Record[Idx++]) { 489 CD->NumCtorInitializers = Record[Idx++] [all...] |
/external/swiftshader/third_party/LLVM/lib/VMCore/ |
DebugLoc.cpp | 193 int &Idx = ScopeRecordIdx[Scope]; 194 if (Idx) return Idx; 198 return Idx = ExistingIdx; 208 Idx = ScopeRecords.size()+1; 209 ScopeRecords.push_back(DebugRecVH(Scope, this, Idx)); 210 return Idx; 216 int &Idx = ScopeInlinedAtIdx[std::make_pair(Scope, IA)]; 217 if (Idx) return Idx; [all...] |
/external/llvm/include/llvm/ADT/ |
PackedVector.h | 30 static T getValue(const BitVectorTy &Bits, unsigned Idx) { 33 val = T(val | ((Bits[(Idx << (BitNum-1)) + i] ? 1UL : 0UL) << i)); 37 static void setValue(BitVectorTy &Bits, unsigned Idx, T val) { 40 Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i); 47 static T getValue(const BitVectorTy &Bits, unsigned Idx) { 50 val = T(val | ((Bits[(Idx << (BitNum-1)) + i] ? 1UL : 0UL) << i)); 51 if (Bits[(Idx << (BitNum-1)) + BitNum-1]) 56 static void setValue(BitVectorTy &Bits, unsigned Idx, T val) { 59 Bits.set((Idx << (BitNum-1)) + BitNum-1); 63 Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i) [all...] |
SparseMultiSet.h | 164 unsigned Idx = FreelistIdx; 165 unsigned NextFree = Dense[Idx].Next; 166 assert(Dense[Idx].isTombstone() && "Non-tombstone free?"); 168 Dense[Idx] = SMSNode(V, Prev, Next); 171 return Idx; 175 void makeTombstone(unsigned Idx) { 176 Dense[Idx].Prev = SMSNode::INVALID; 177 Dense[Idx].Next = FreelistIdx; 178 FreelistIdx = Idx; 222 unsigned Idx; [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/ADT/ |
PackedVector.h | 30 static T getValue(const llvm::BitVector &Bits, unsigned Idx) { 33 val = T(val | ((Bits[(Idx << (BitNum-1)) + i] ? 1UL : 0UL) << i)); 37 static void setValue(llvm::BitVector &Bits, unsigned Idx, T val) { 40 Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i); 47 static T getValue(const llvm::BitVector &Bits, unsigned Idx) { 50 val = T(val | ((Bits[(Idx << (BitNum-1)) + i] ? 1UL : 0UL) << i)); 51 if (Bits[(Idx << (BitNum-1)) + BitNum-1]) 56 static void setValue(llvm::BitVector &Bits, unsigned Idx, T val) { 59 Bits.set((Idx << (BitNum-1)) + BitNum-1); 63 Bits[(Idx << (BitNum-1)) + i] = val & (T(1) << i) [all...] |
/external/llvm/lib/Target/Hexagon/ |
HexagonBlockRanges.h | 56 IndexType(unsigned Idx) : Index(Idx) {} 59 bool operator== (IndexType Idx) const; 61 bool operator!= (IndexType Idx) const; 63 bool operator< (unsigned Idx) const; 64 bool operator< (IndexType Idx) const; 65 bool operator<= (IndexType Idx) const; 68 bool operator> (IndexType Idx) const; 69 bool operator>= (IndexType Idx) const; 121 MachineInstr *getInstr(IndexType Idx) const [all...] |
/external/llvm/include/llvm/Support/ |
ArrayRecycler.h | 43 // Remove an entry from the free list in Bucket[Idx] and return it. 45 T *pop(unsigned Idx) { 46 if (Idx >= Bucket.size()) 48 FreeList *Entry = Bucket[Idx]; 51 Bucket[Idx] = Entry->Next; 55 // Add an entry to the free list at Bucket[Idx]. 56 void push(unsigned Idx, T *Ptr) { 59 if (Idx >= Bucket.size()) 60 Bucket.resize(size_t(Idx) + 1); 61 Entry->Next = Bucket[Idx]; [all...] |
/external/llvm/lib/MC/ |
MCRegisterInfo.cpp | 26 unsigned MCRegisterInfo::getSubReg(unsigned Reg, unsigned Idx) const { 27 assert(Idx && Idx < getNumSubRegIndices() && 33 if (*SRI == Idx) 49 unsigned MCRegisterInfo::getSubRegIdxSize(unsigned Idx) const { 50 assert(Idx && Idx < getNumSubRegIndices() && 52 return SubRegIdxRanges[Idx].Size; 55 unsigned MCRegisterInfo::getSubRegIdxOffset(unsigned Idx) const { 56 assert(Idx && Idx < getNumSubRegIndices() & [all...] |
/external/compiler-rt/lib/esan/ |
esan_circular_buffer.h | 48 T &operator[](uptr Idx) { 49 CHECK_LT(Idx, Count); 50 uptr ArrayIdx = (StartIdx + Idx) % Capacity; 53 const T &operator[](uptr Idx) const { 54 CHECK_LT(Idx, Count); 55 uptr ArrayIdx = (StartIdx + Idx) % Capacity;
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/external/llvm/include/llvm/CodeGen/ |
RegisterClassInfo.h | 134 unsigned getRegPressureSetLimit(unsigned Idx) const { 135 if (!PSetLimits[Idx]) 136 PSetLimits[Idx] = computePSetLimit(Idx); 137 return PSetLimits[Idx]; 141 unsigned computePSetLimit(unsigned Idx) const;
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/prebuilts/clang/host/linux-x86/clang-3859424/prebuilt_include/llvm/lib/Fuzzer/ |
FuzzerCorpus.h | 61 const Unit &operator[] (size_t Idx) const { return Inputs[Idx]->U; } 91 size_t Idx = static_cast<size_t>(CorpusDistribution(Rand.Get_mt19937())); 92 assert(Idx < Inputs.size()); 93 return Idx; 117 void DeleteInput(size_t Idx) { 118 InputInfo &II = *Inputs[Idx]; 123 Printf("EVICTED %zd\n", Idx); 126 bool AddFeature(size_t Idx, uint32_t NewSize, bool Shrink) { 128 Idx = Idx % kFeatureSetSize [all...] |
FuzzerValueBitMap.h | 33 uintptr_t Idx = Value < kMapSizeInBits ? Value : Value % kMapSizeInBits; 34 uintptr_t WordIdx = Idx / kBitsInWord; 35 uintptr_t BitIdx = Idx % kBitsInWord; 42 inline bool Get(uintptr_t Idx) { 43 assert(Idx < kMapSizeInBits); 44 uintptr_t WordIdx = Idx / kBitsInWord; 45 uintptr_t BitIdx = Idx % kBitsInWord;
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FuzzerTracePC.h | 35 void Insert(size_t Idx, T Arg1, T Arg2) { 36 Idx = Idx % kSize; 37 Table[Idx].A = Arg1; 38 Table[Idx].B = Arg2; 89 uintptr_t GetPC(size_t Idx) { 90 assert(Idx < GetNumPCs()); 91 return PCs[Idx];
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/external/swiftshader/third_party/LLVM/include/llvm/ |
Attributes.h | 170 static AttributeWithIndex get(unsigned Idx, Attributes Attrs) { 172 P.Index = Idx; 214 AttrListPtr addAttr(unsigned Idx, Attributes Attrs) const; 219 AttrListPtr removeAttr(unsigned Idx, Attributes Attrs) const; 226 Attributes getParamAttributes(unsigned Idx) const { 227 assert (Idx && Idx != ~0U && "Invalid parameter index!"); 228 return getAttributes(Idx); 244 bool paramHasAttr(unsigned Idx, Attributes Attr) const { 245 return (getAttributes(Idx) & Attr) != 0 [all...] |
User.h | 74 template <int Idx, typename U> static Use &OpFrom(const U *that) { 75 return Idx < 0 76 ? OperandTraits<U>::op_end(const_cast<U*>(that))[Idx] 77 : OperandTraits<U>::op_begin(const_cast<U*>(that))[Idx]; 79 template <int Idx> Use &Op() { 80 return OpFrom<Idx>(this); 82 template <int Idx> const Use &Op() const { 83 return OpFrom<Idx>(this);
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
ARMMCTargetDesc.cpp | 42 unsigned Idx = 0; 47 Idx = 4; 51 Idx = 6; 55 if (Idx) { 56 unsigned SubVer = TT[Idx]; 58 if (Len >= Idx+2 && TT[Idx+1] == 'm') { 61 } else if (Len >= Idx+3 && TT[Idx+1] == 'e'&& TT[Idx+2] == 'm') [all...] |
/external/llvm/utils/TableGen/ |
CodeGenSchedule.h | 61 CodeGenSchedRW(unsigned Idx, Record *Def) 62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { 75 CodeGenSchedRW(unsigned Idx, bool Read, ArrayRef<unsigned> Seq, 77 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false), 174 // ItinDefList orders this processor's InstrItinData records by SchedClass idx. 204 CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef, 206 Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {} 318 const CodeGenSchedRW &getSchedWrite(unsigned Idx) const { 319 assert(Idx < SchedWrites.size() && "bad SchedWrite index"); 320 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite") [all...] |
/device/linaro/bootloader/edk2/CorebootModulePkg/Library/CbParseLib/ |
CbParseLib.c | 62 UINTN Idx;
67 for(Idx = 0; Idx < Length; Idx++) {
68 TmpValue = TmpPtr[Idx];
69 if (Idx % 2 == 1) {
106 UINTN Idx;
111 for (Idx = 0; Idx < 4096; Idx += 16, TmpPtr += 16) { [all...] |
/external/llvm/lib/Target/AVR/ |
AVRMachineFunctionInfo.h | 64 void setVarArgsFrameIndex(int Idx) { VarArgsFrameIndex = Idx; }
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