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    Searched refs:MO2 (Results 1 - 13 of 13) sorted by null

  /external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp 62 const MCOperand &MO2 = MI->getOperand(2);
72 O << ", " << getRegisterName(MO2.getReg());
82 const MCOperand &MO2 = MI->getOperand(2);
84 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
91 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
96 O << ", #" << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm()));
243 const MCOperand &MO2 = MI->getOperand(OpNum+1);
254 O << ' ' << getRegisterName(MO2.getReg());
261 const MCOperand &MO2 = MI->getOperand(OpNum+1);
266 ARM_AM::ShiftOpc ShOpc = ARM_AM::getSORegShOp(MO2.getImm())
    [all...]
  /external/llvm/lib/Target/ARM/InstPrinter/
ARMInstPrinter.cpp 82 const MCOperand &MO2 = MI->getOperand(2);
95 printRegName(O, MO2.getReg());
105 const MCOperand &MO2 = MI->getOperand(2);
107 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm()));
116 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) {
122 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">");
346 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
358 printRegName(O, MO2.getReg());
366 const MCOperand &MO2 = MI->getOperand(OpNum + 1);
371 printRegImmShift(O, ARM_AM::getSORegShOp(MO2.getImm())
    [all...]
  /external/llvm/lib/Target/X86/
X86OptimizeLEAs.cpp 56 const MachineOperand &MO2);
61 const MachineOperand &MO2);
182 const MachineOperand &MO2) {
183 return MO1.isIdenticalTo(MO2) &&
196 const MachineOperand &MO2) {
197 assert(isValidDispOp(MO1) && isValidDispOp(MO2) &&
199 return (MO1.isImm() && MO2.isImm()) ||
200 (MO1.isCPI() && MO2.isCPI() && MO1.getIndex() == MO2.getIndex()) ||
201 (MO1.isJTI() && MO2.isJTI() && MO1.getIndex() == MO2.getIndex()) |
    [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/
ARMMCCodeEmitter.cpp 691 const MCOperand &MO2 = MI.getOperand(OpIdx + 1);
693 unsigned Rm = getARMRegisterNumbering(MO2.getReg());
    [all...]
  /external/mesa3d/src/gallium/drivers/radeon/
R600InstrInfo.cpp 424 MachineOperand &MO2 = Cond[2];
425 switch (MO2.getReg()) {
427 MO2.setReg(AMDGPU::PRED_SEL_ONE);
430 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
  /external/llvm/lib/Target/ARM/MCTargetDesc/
ARMMCCodeEmitter.cpp     [all...]
  /external/swiftshader/third_party/LLVM/lib/Target/ARM/
ARMCodeEmitter.cpp     [all...]
ARMAsmPrinter.cpp     [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonAsmPrinter.cpp 402 MCOperand &MO2 = MappedInst.getOperand(2);
403 MCExpr const *Expr = MO2.getExpr();
  /external/llvm/lib/CodeGen/
ScheduleDAGInstrs.cpp 706 for (const MachineOperand &MO2 : MI->operands()) {
707 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
    [all...]
  /external/llvm/lib/Target/Hexagon/AsmParser/
HexagonAsmParser.cpp     [all...]
  /external/llvm/lib/Target/AMDGPU/
R600InstrInfo.cpp 964 MachineOperand &MO2 = Cond[2];
965 switch (MO2.getReg()) {
967 MO2.setReg(AMDGPU::PRED_SEL_ONE);
970 MO2.setReg(AMDGPU::PRED_SEL_ZERO);
    [all...]
  /external/swiftshader/third_party/LLVM/lib/CodeGen/
LiveIntervalAnalysis.cpp 315 MachineOperand &MO2 = mi->getOperand(i);
316 if (MO2.isReg() && MO2.getReg() == interval.reg && MO2.getSubReg())
317 MO2.setIsUndef();
    [all...]

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