| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 26 /// MVT - Machine Value Type. Every type that is supported natively by some
28 /// type can be represented by an MVT.
29 class MVT {
140 // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
181 LLVM_CONSTEXPR MVT() : SimpleTy(INVALID_SIMPLE_VALUE_TYPE) {}
182 LLVM_CONSTEXPR MVT(SimpleValueType SVT) : SimpleTy(SVT) { }
184 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
185 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
186 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
187 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy;
[all...] |
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 129 case MVT::i1: return "i1";
130 case MVT::i8: return "i8";
131 case MVT::i16: return "i16";
132 case MVT::i32: return "i32";
133 case MVT::i64: return "i64";
134 case MVT::i128: return "i128";
135 case MVT::f16: return "f16";
136 case MVT::f32: return "f32";
137 case MVT::f64: return "f64";
138 case MVT::f80: return "f80"
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCCallingConv.h | 23 inline bool CC_PPC_AnyReg_Error(unsigned &, MVT &, MVT &,
|
| PPCCCState.cpp | 20 if (I.ArgVT == llvm::MVT::ppcf128)
30 if (I.ArgVT == llvm::MVT::ppcf128) {
|
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 93 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Ty);
119 { ISD::SRA, MVT::v4i64, 4 }, // 2 x psrad + shuffle.
121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
122 { ISD::UDIV, MVT::v16i16, 6 }, // vpmulhuw sequence
123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
124 { ISD::UDIV, MVT::v8i32, 15 }, // vpmuludq sequence
135 { ISD::SHL, MVT::v16i32, 1 },
136 { ISD::SRL, MVT::v16i32, 1 },
137 { ISD::SRA, MVT::v16i32, 1 },
138 { ISD::SHL, MVT::v8i64, 1 }
[all...] |
| X86CallingConv.h | 24 inline bool CC_X86_32_VectorCallIndirect(unsigned &ValNo, MVT &ValVT,
25 MVT &LocVT,
30 LocVT = MVT::i32;
37 inline bool CC_X86_AnyReg_Error(unsigned &, MVT &, MVT &,
46 inline bool CC_X86_32_MCUInReg(unsigned &ValNo, MVT &ValVT,
47 MVT &LocVT,
|
| X86ShuffleDecodeConstantPool.h | 26 class MVT;
43 void DecodeVPERMVMask(const Constant *C, MVT VT,
47 void DecodeVPERMV3Mask(const Constant *C, MVT VT,
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| ValueTypes.h | 29 /// MVT - Machine Value Type. Every type that is supported natively by some
31 /// type can be represented by a MVT.
32 class MVT {
93 // MVT::MAX_ALLOWED_VALUETYPE is used for asserts and to size bit vectors
134 MVT() : SimpleTy((SimpleValueType)(INVALID_SIMPLE_VALUE_TYPE)) {}
135 MVT(SimpleValueType SVT) : SimpleTy(SVT) { }
137 bool operator>(const MVT& S) const { return SimpleTy > S.SimpleTy; }
138 bool operator<(const MVT& S) const { return SimpleTy < S.SimpleTy; }
139 bool operator==(const MVT& S) const { return SimpleTy == S.SimpleTy; }
140 bool operator!=(const MVT& S) const { return SimpleTy != S.SimpleTy;
[all...] |
| /external/swiftshader/third_party/LLVM/lib/VMCore/ |
| ValueTypes.cpp | 105 case MVT::i1: return "i1";
106 case MVT::i8: return "i8";
107 case MVT::i16: return "i16";
108 case MVT::i32: return "i32";
109 case MVT::i64: return "i64";
110 case MVT::i128: return "i128";
111 case MVT::f32: return "f32";
112 case MVT::f64: return "f64";
113 case MVT::f80: return "f80";
114 case MVT::f128: return "f128"
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 83 { ISD::FP_ROUND, MVT::v2f64, 2 },
84 { ISD::FP_EXTEND, MVT::v2f32, 2 },
85 { ISD::FP_EXTEND, MVT::v4f32, 4 }
90 std::pair<int, MVT> LT = TLI->getTypeLegalizationCost(DL, Src);
105 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
106 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 },
107 { ISD::SIGN_EXTEND, MVT::v2i64, MVT::v2i32, 1 }
[all...] |
| /external/llvm/lib/Target/X86/Utils/ |
| X86ShuffleDecode.h | 26 class MVT;
35 void DecodeInsertElementMask(MVT VT, unsigned Idx, unsigned Len,
46 void DecodeMOVSLDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
48 void DecodeMOVSHDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
50 void DecodeMOVDDUPMask(MVT VT, SmallVectorImpl<int> &ShuffleMask);
52 void DecodePSLLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
54 void DecodePSRLDQMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
56 void DecodePALIGNRMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
61 void DecodePSHUFMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask);
66 void DecodePSHUFHWMask(MVT VT, unsigned Imm, SmallVectorImpl<int> &ShuffleMask)
[all...] |
| /external/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| WebAssemblyTargetStreamer.h | 33 virtual void emitParam(ArrayRef<MVT> Types) = 0;
35 virtual void emitResult(ArrayRef<MVT> Types) = 0;
37 virtual void emitLocal(ArrayRef<MVT> Types) = 0;
42 SmallVectorImpl<MVT> &SignatureVTs,
55 void emitParam(ArrayRef<MVT> Types) override;
56 void emitResult(ArrayRef<MVT> Types) override;
57 void emitLocal(ArrayRef<MVT> Types) override;
60 SmallVectorImpl<MVT> &SignatureVTs,
69 void emitParam(ArrayRef<MVT> Types) override;
70 void emitResult(ArrayRef<MVT> Types) override
[all...] |
| WebAssemblyTargetStreamer.cpp | 38 static void PrintTypes(formatted_raw_ostream &OS, ArrayRef<MVT> Types) {
40 for (MVT Type : Types) {
50 void WebAssemblyTargetAsmStreamer::emitParam(ArrayRef<MVT> Types) {
55 void WebAssemblyTargetAsmStreamer::emitResult(ArrayRef<MVT> Types) {
60 void WebAssemblyTargetAsmStreamer::emitLocal(ArrayRef<MVT> Types) {
68 StringRef name, SmallVectorImpl<MVT> &SignatureVTs, size_t NumResults) {
79 static void EncodeTypes(MCStreamer &Streamer, ArrayRef<MVT> Types) {
81 for (MVT Type : Types)
85 void WebAssemblyTargetELFStreamer::emitParam(ArrayRef<MVT> Types) {
90 void WebAssemblyTargetELFStreamer::emitResult(ArrayRef<MVT> Types)
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 191 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 },
192 { ISD::TRUNCATE, MVT::v4i32, MVT::v4i64, 0 },
193 { ISD::TRUNCATE, MVT::v8i8, MVT::v8i32, 3 },
194 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
197 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }
[all...] |
| AArch64ISelDAGToDAG.cpp | 276 Val = CurDAG->getTargetConstant(Immed, dl, MVT::i32);
277 Shift = CurDAG->getTargetConstant(ShVal, dl, MVT::i32);
302 if (N.getValueType() == MVT::i32)
310 return SelectArithImmed(CurDAG->getConstant(Immed, SDLoc(N), MVT::i32), Val,
357 Shift = CurDAG->getTargetConstant(ShVal, SDLoc(N), MVT::i32);
376 if (!IsLoadStore && SrcVT == MVT::i8)
378 else if (!IsLoadStore && SrcVT == MVT::i16)
380 else if (SrcVT == MVT::i32)
382 assert(SrcVT != MVT::i64 && "extend from 64-bits?");
388 if (!IsLoadStore && SrcVT == MVT::i8
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 36 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
38 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
39 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
42 StringRef llvm::getName(MVT::SimpleValueType T) {
44 case MVT::Other: return "UNKNOWN";
45 case MVT::iPTR: return "TLI.getPointerTy()";
46 case MVT::iPTRAny: return "TLI.getPointerTy()";
51 StringRef llvm::getEnumName(MVT::SimpleValueType T) {
53 case MVT::Other: return "MVT::Other"
[all...] |
| /external/llvm/include/llvm/Target/ |
| CostTable.h | 26 MVT::SimpleValueType Type;
32 int ISD, MVT Ty) {
46 MVT::SimpleValueType Dst;
47 MVT::SimpleValueType Src;
55 int ISD, MVT Dst, MVT Src) {
|
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUISelLowering.cpp | 46 if (VT==MVT::i1) retval=3;
47 if (VT==MVT::i8) retval=3;
48 if (VT==MVT::i16) retval=2;
107 addRegisterClass(MVT::i8, SPU::R8CRegisterClass);
108 addRegisterClass(MVT::i16, SPU::R16CRegisterClass);
109 addRegisterClass(MVT::i32, SPU::R32CRegisterClass);
110 addRegisterClass(MVT::i64, SPU::R64CRegisterClass);
111 addRegisterClass(MVT::f32, SPU::R32FPRegisterClass);
112 addRegisterClass(MVT::f64, SPU::R64FPRegisterClass);
113 addRegisterClass(MVT::i128, SPU::GPRCRegisterClass)
2749 MVT mvt = Op0VT == MVT::i64 ? MVT::v2i64 : MVT::v4i32; local
[all...] |
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 51 (int)MVT::i8,
52 (int)MVT::i16,
53 (int)MVT::i32,
54 (int)MVT::f32,
55 (int)MVT::f64,
56 (int)MVT::i64,
57 (int)MVT::v2i8,
58 (int)MVT::v4i8,
59 (int)MVT::v2i16,
60 (int)MVT::v4i16
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 102 static bool IsHvxVectorType(MVT ty);
105 CC_Hexagon(unsigned ValNo, MVT ValVT,
106 MVT LocVT, CCValAssign::LocInfo LocInfo,
110 CC_Hexagon32(unsigned ValNo, MVT ValVT,
111 MVT LocVT, CCValAssign::LocInfo LocInfo,
115 CC_Hexagon64(unsigned ValNo, MVT ValVT,
116 MVT LocVT, CCValAssign::LocInfo LocInfo,
120 CC_HexagonVector(unsigned ValNo, MVT ValVT,
121 MVT LocVT, CCValAssign::LocInfo LocInfo,
125 RetCC_Hexagon(unsigned ValNo, MVT ValVT
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMCallingConv.h | 29 static bool f64AssignAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
59 static bool CC_ARM_APCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
65 if (LocVT == MVT::v2f64 &&
72 static bool f64AssignAAPCS(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
107 static bool CC_ARM_AAPCS_Custom_f64(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
113 if (LocVT == MVT::v2f64 &
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXISelLowering.cpp | 38 addRegisterClass(MVT::i1, PTX::RegPredRegisterClass);
39 addRegisterClass(MVT::i16, PTX::RegI16RegisterClass);
40 addRegisterClass(MVT::i32, PTX::RegI32RegisterClass);
41 addRegisterClass(MVT::i64, PTX::RegI64RegisterClass);
42 addRegisterClass(MVT::f32, PTX::RegF32RegisterClass);
43 addRegisterClass(MVT::f64, PTX::RegF64RegisterClass);
55 setLoadExtAction(ISD::EXTLOAD, MVT::i16, Expand);
56 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
57 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand);
61 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand)
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 34 static bool allocateKernArg(unsigned ValNo, MVT ValVT, MVT LocVT,
55 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
63 return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
71 setOperationAction(ISD::LOAD, MVT::f32, Promote);
72 AddPromotedToType(ISD::LOAD, MVT::f32, MVT::i32);
74 setOperationAction(ISD::LOAD, MVT::v2f32, Promote);
75 AddPromotedToType(ISD::LOAD, MVT::v2f32, MVT::v2i32)
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
| SparcISelLowering.cpp | 37 static bool CC_Sparc_Assign_SRet(unsigned &ValNo, MVT &ValVT,
38 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
50 static bool CC_Sparc_Assign_f64(unsigned &ValNo, MVT &ValVT,
51 MVT &LocVT, CCValAssign::LocInfo &LocInfo,
136 SDValue RetAddrOffsetNode = DAG.getConstant(RetAddrOffset, MVT::i32);
139 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
141 return DAG.getNode(SPISD::RET_FLAG, dl, MVT::Other, Chain,
175 SDValue FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
176 SDValue Arg = DAG.getLoad(MVT::i32, dl, Chain, FIPtr,
185 assert(VA.getLocVT() == MVT::f64)
[all...] |
| /external/swiftshader/third_party/LLVM/utils/TableGen/ |
| CodeGenTarget.cpp | 34 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen
36 MVT::SimpleValueType llvm::getValueType(Record *Rec) {
37 return (MVT::SimpleValueType)Rec->getValueAsInt("Value");
40 std::string llvm::getName(MVT::SimpleValueType T) {
42 case MVT::Other: return "UNKNOWN";
43 case MVT::iPTR: return "TLI.getPointerTy()";
44 case MVT::iPTRAny: return "TLI.getPointerTy()";
49 std::string llvm::getEnumName(MVT::SimpleValueType T) {
51 case MVT::Other: return "MVT::Other"
[all...] |
