| /external/llvm/include/llvm/Target/ |
| TargetOpcodes.h | 23 #define HANDLE_TARGET_OPCODE(OPC, NUM) OPC = NUM,
24 #define HANDLE_TARGET_OPCODE_MARKER(IDENT, OPC) IDENT = OPC,
|
| /bionic/libc/upstream-netbsd/lib/libc/regex/ |
| regex2.h | 121 #define OPC(n) (((u_int32_t)(n))<<OPSHIFT)
124 #define OEND OPC(1) /* endmarker - */
125 #define OCHAR OPC(2) /* character unsigned char */
126 #define OBOL OPC(3) /* left anchor - */
127 #define OEOL OPC(4) /* right anchor - */
128 #define OANY OPC(5) /* . - */
129 #define OANYOF OPC(6) /* [...] set number */
130 #define OBACK_ OPC(7) /* begin \d paren number */
131 #define O_BACK OPC(8) /* end \d paren number */
132 #define OPLUS_ OPC(9) /* + prefix fwd to suffix *
[all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| dlx-dis.c | 36 #define OPC(x) ((x >> 26) & 0x3F)
39 unsigned char opc, rs1, rs2, rd; variable
106 unsigned char r_opc[] = { OPC(ALUOP) }; /* Fix ME */
152 if (r_opc[idx] != opc)
193 { OPC(LHIOP), "lhi" }, /* Load HI to register. */
194 { OPC(LBOP), "lb" }, /* load byte sign extended. */
195 { OPC(LBUOP), "lbu" }, /* load byte unsigned. */
196 { OPC(LSBUOP),"ldstbu"}, /* load store byte unsigned. */
197 { OPC(LHOP), "lh" }, /* load halfword sign extended. */
198 { OPC(LHUOP), "lhu" }, /* load halfword unsigned. *
[all...] |
| cr16-opc.c | 1 /* cr16-opc.c -- Table of opcodes for the CR16 processor.
29 #define ARITH_BYTE_INST(NAME, OPC, OP1) \
31 {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{uimm4_1,20}, {regr,16}}}, \
33 {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}, \
35 {NAME, 1, OPC+0x1, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
38 #define ARITH1_BYTE_INST(NAME, OPC, OP1) \
40 {NAME, 2, (OPC<<4)+0xB, 20, ARITH_BYTE_INS, {{OP1,0}, {regr,16}}}
79 #define ARITH_BYTE_INST1(NAME, OPC) \
81 {NAME, 1, OPC, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
87 #define ARITH_BYTE_INST2(NAME, OPC) \
[all...] |
| crx-opc.c | 1 /* crx-opc.c -- Table of opcodes for the CRX processor.
31 #define ARITH_BYTE_INST(NAME, OPC) \
33 {NAME, 1, OPC, 24, ARITH_BYTE_INS | CST4MAP, {{cst4,20}, {regr,16}}}, \
35 {NAME, 2, (OPC<<4)+0xE, 20, ARITH_BYTE_INS | CST4MAP, {{i16,0}, {regr,16}}}, \
37 {NAME, 1, OPC+0x40, 24, ARITH_BYTE_INS, {{regr,20}, {regr,16}}}
64 #define ARITH_INST(NAME, OPC) \
66 {NAME, 1, OPC, 24, ARITH_INS | CST4MAP, {{cst4,20}, {regr,16}}}, \
68 {NAME, 2, (OPC<<4)+0xE, 20, ARITH_INS | CST4MAP, {{i16,0}, {regr,16}}}, \
70 {NAME, 3, (OPC<<4)+0xF, 20, ARITH_INS, {{i32,0}, {regr,16}}}, \
72 {NAME, 1, OPC+0x40, 24, ARITH_INS, {{regr,20}, {regr,16}}
[all...] |
| cgen.sh | 22 # Generate CGEN opcode files: arch-desc.[ch], arch-opc.[ch],
27 # arch-file opc-file options [extrafiles]
36 # OPC-FILE is the name of the .opc file (including path).
90 rm -f ${tmp}-opc.h ${tmp}-opc.h1
91 rm -f ${tmp}-opc.c ${tmp}-opc.c1
99 ${cgen} ${cgendir}/cgen-opc.scm \
105 -OPC ${opcfile}
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| rx-parse.y | 1001 #define OPC(x) { #x, x, IS_OPCODE }
1002 OPC(ABS),
1003 OPC(ADC),
1004 OPC(ADD),
1006 OPC(BCLR),
1007 OPC(BCND),
1008 OPC(BMCND),
1009 OPC(BNOT),
1010 OPC(BRA),
1011 OPC(BRK)
[all...] |
| rl78-parse.y | 1256 #define OPC(x) { #x, x, IS_OPCODE }
1258 OPC(ADD),
1259 OPC(ADDC),
1260 OPC(ADDW),
1262 OPC(AND1),
1263 OPC(BC),
1264 OPC(BF),
1265 OPC(BH),
1266 OPC(BNC),
1267 OPC(BNH)
[all...] |
| /external/llvm/include/llvm/IR/ |
| Instruction.h | 476 #define HANDLE_TERM_INST(N, OPC, CLASS) OPC = N,
483 #define HANDLE_BINARY_INST(N, OPC, CLASS) OPC = N,
490 #define HANDLE_MEMORY_INST(N, OPC, CLASS) OPC = N,
497 #define HANDLE_CAST_INST(N, OPC, CLASS) OPC = N,
504 #define HANDLE_FUNCLETPAD_INST(N, OPC, CLASS) OPC = N
[all...] |
| InstrTypes.h | 370 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
371 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
373 return Create(Instruction::OPC, V1, V2, Name);\
376 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
377 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
379 return Create(Instruction::OPC, V1, V2, Name, BB);\
382 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
383 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
385 return Create(Instruction::OPC, V1, V2, Name, I);\
389 static BinaryOperator *CreateWithCopiedFlags(BinaryOps Opc,
[all...] |
| /external/swiftshader/third_party/LLVM/include/llvm/ |
| Instruction.h | 312 #define HANDLE_TERM_INST(N, OPC, CLASS) OPC = N,
319 #define HANDLE_BINARY_INST(N, OPC, CLASS) OPC = N,
326 #define HANDLE_MEMORY_INST(N, OPC, CLASS) OPC = N,
333 #define HANDLE_CAST_INST(N, OPC, CLASS) OPC = N,
340 #define HANDLE_OTHER_INST(N, OPC, CLASS) OPC = N
[all...] |
| InstrTypes.h | 177 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
178 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
180 return Create(Instruction::OPC, V1, V2, Name);\
183 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
184 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
186 return Create(Instruction::OPC, V1, V2, Name, BB);\
189 #define HANDLE_BINARY_INST(N, OPC, CLASS) \
190 static BinaryOperator *Create##OPC(Value *V1, Value *V2, \
192 return Create(Instruction::OPC, V1, V2, Name, I);\
196 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2
[all...] |
| /external/libpcap/ |
| tokdefs.h | 157 OPC = 367,
279 #define OPC 367
|
| grammar.y | 312 %token SIO OPC DPC SLS HSIO HOPC HDPC HSLS
724 | OPC { $$.mtp3fieldtype = M_OPC; }
|
| grammar.c | 472 OPC = 367,
594 #define OPC 367
994 "RADIO", "FISU", "LSSU", "MSU", "HFISU", "HLSSU", "HMSU", "SIO", "OPC",
[all...] |
| scanner.l | 310 opc return OPC;
|
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| cr16.h | 412 as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
414 #define BIN(OPC,SHIFT) (OPC << SHIFT)
|
| crx.h | 398 as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT)
400 #define BIN(OPC,SHIFT) (OPC << SHIFT)
|
| aarch64.h | 72 #define AARCH64_OPCODE_HAS_FEATURE(OPC,FEAT) \
73 (((OPC) & (FEAT)) != 0)
531 /* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
|
| /external/valgrind/auxprogs/ |
| s390-check-opcodes.pl | 8 # It utilizes <binutils>/opcodes/s390-opc.txt and
10 # - identify new opcodes that are present in s390-opc.txt
11 # (s390-opc.txt is the golden list)
18 die "usage: s390-check-opcodes s390-opcodes.csv s390-opc.txt guest_s390_toIR.c\n";
33 # Read s390-opc.txt (binutils)
35 open(OPC, "$opc_file") || die "cannot open $opc_file\n";
36 while (my $line = <OPC>) {
116 close(OPC);
202 foreach my $opc (keys %opc_desc) {
203 if (! $csv_desc{$opc}) {
[all...] |
| /external/autotest/client/cros/cellular/ |
| scpi.py | 110 self.Query('*OPC?') # Wait for operation complete
144 self.Query('*OPC?')
|
| /toolchain/binutils/binutils-2.25/bfd/ |
| xtensa-isa.c | 652 #define CHECK_OPCODE(INTISA,OPC,ERRVAL) \
654 if ((OPC) < 0 || (OPC) >= (INTISA)->num_opcodes) \
701 xtensa_opcode opc;
708 opc = (intisa->slots[slot_id].opcode_decode_fn) (slotbuf);
709 if (opc != XTENSA_UNDEFINED)
710 return opc;
720 xtensa_insnbuf slotbuf, xtensa_opcode opc)
728 CHECK_OPCODE (intisa, opc, -1);
731 encode_fn = intisa->opcodes[opc].encode_fns[slot_id]
697 xtensa_opcode opc; local
[all...] |
| /prebuilts/go/darwin-x86/src/cmd/compile/internal/gc/ |
| opnames.go | 165 OPC: "PC",
|
| /prebuilts/go/linux-x86/src/cmd/compile/internal/gc/ |
| opnames.go | 165 OPC: "PC",
|
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 304 #define HANDLE_TARGET_OPCODE(OPC, NUM) #OPC,
|
