| /external/javassist/src/main/javassist/bytecode/ |
| Mnemonic.java | 21 * <p>This interface has been separated from javassist.bytecode.Opcode
23 * interface were merged with Opcode, extra memory would be unnecessary
26 * @see Opcode
31 * The instruction names (mnemonics) sorted by the opcode.
37 String[] OPCODE = {
|
| /toolchain/binutils/binutils-2.25/opcodes/ |
| spu-opc.c | 1 /* SPU opcode list
22 #include "opcode/spu.h"
24 /* This file holds the Spu opcode table */
30 id_tag mode mode type opcode mnemonic asmtype dependency FPU L/S? branch? instruction
36 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
37 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
38 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
39 { MACFORMAT, OPCODE, MNEMONIC, ASMFORMAT },
40 #include "opcode/spu-insns.h"
|
| /external/llvm/lib/Analysis/ |
| InstCount.cpp | 31 #define HANDLE_INST(N, OPCODE, CLASS) \
32 STATISTIC(Num ## OPCODE ## Inst, "Number of " #OPCODE " insts");
44 #define HANDLE_INST(N, OPCODE, CLASS) \
45 void visit##OPCODE(CLASS &) { ++Num##OPCODE##Inst; ++TotalInsts; }
|
| /external/swiftshader/third_party/LLVM/lib/Analysis/ |
| InstCount.cpp | 30 #define HANDLE_INST(N, OPCODE, CLASS) \
31 STATISTIC(Num ## OPCODE ## Inst, "Number of " #OPCODE " insts");
43 #define HANDLE_INST(N, OPCODE, CLASS) \
44 void visit##OPCODE(CLASS &) { ++Num##OPCODE##Inst; ++TotalInsts; }
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/immutable/instruction/ |
| ImmutableArrayPayload.java | 36 import org.jf.dexlib2.Opcode;
45 public static final Opcode OPCODE = Opcode.ARRAY_PAYLOAD;
52 super(OPCODE);
59 super(OPCODE);
80 @Override public Format getFormat() { return OPCODE.format; }
|
| ImmutablePackedSwitchPayload.java | 36 import org.jf.dexlib2.Opcode;
46 public static final Opcode OPCODE = Opcode.PACKED_SWITCH_PAYLOAD;
51 super(OPCODE);
58 super(OPCODE);
74 @Override public Format getFormat() { return OPCODE.format; }
|
| ImmutableSparseSwitchPayload.java | 36 import org.jf.dexlib2.Opcode;
46 public static final Opcode OPCODE = Opcode.SPARSE_SWITCH_PAYLOAD;
51 super(OPCODE);
57 super(OPCODE);
73 @Override public Format getFormat() { return OPCODE.format; }
|
| /external/valgrind/none/tests/ppc32/ |
| opcodes.h | 28 #define X20_ASM(OPCODE, TH, RA, RB, XO, RES) \
30 "(" #OPCODE "<<" X20_OPCODE_OFFSET ")" "+" \
37 #define X20(OPCODE, TH, RA, RB, XO, RES) X20_ASM(OPCODE, TH, RA, RB, XO, RES)
|
| /frameworks/rs/rsov/compiler/spirit/ |
| visitor.h | 35 #define HANDLE_INSTRUCTION(OPCODE, INST_CLASS) class INST_CLASS;
53 #define HANDLE_INSTRUCTION(OPCODE, INST_CLASS) \
74 #define HANDLE_INSTRUCTION(OPCODE, INST_CLASS) virtual void visit(INST_CLASS *);
85 #define HANDLE_INSTRUCTION(OPCODE, INST_CLASS) \
|
| visitor.cpp | 44 #define HANDLE_INSTRUCTION(OPCODE, INST_CLASS) \
|
| transformer.h | 61 #define HANDLE_INSTRUCTION(OPCODE, INST_CLASS) \
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/builder/instruction/ |
| BuilderArrayPayload.java | 36 import org.jf.dexlib2.Opcode;
45 public static final Opcode OPCODE = Opcode.ARRAY_PAYLOAD;
52 super(OPCODE);
61 @Override public Format getFormat() { return OPCODE.format; }
|
| BuilderPackedSwitchPayload.java | 37 import org.jf.dexlib2.Opcode;
47 public static final Opcode OPCODE = Opcode.PACKED_SWITCH_PAYLOAD;
53 super(OPCODE);
68 @Override public Format getFormat() { return OPCODE.format; }
|
| BuilderSparseSwitchPayload.java | 38 import org.jf.dexlib2.Opcode;
48 public static final Opcode OPCODE = Opcode.SPARSE_SWITCH_PAYLOAD;
53 super(OPCODE);
69 @Override public Format getFormat() { return OPCODE.format; }
|
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/dexbacked/instruction/ |
| DexBackedArrayPayload.java | 34 import org.jf.dexlib2.Opcode;
44 public static final Opcode OPCODE = Opcode.ARRAY_PAYLOAD;
55 super(dexFile, OPCODE, instructionStart);
|
| /external/swiftshader/third_party/LLVM/test/MC/MBlaze/ |
| mblaze_pattern.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
|
| mblaze_shift.s | 6 # TYPE A: OPCODE RD RA RB FLAGS
|
| /external/swiftshader/third_party/LLVM/include/llvm/Support/ |
| InstVisitor.h | 24 #define HANDLE_INST(NUM, OPCODE, CLASS) class CLASS;
76 /// opcode.
119 #define HANDLE_INST(NUM, OPCODE, CLASS) \
120 case Instruction::OPCODE: return \
122 visit##OPCODE(static_cast<CLASS&>(I));
148 // class and opcode name are the exact same. Because of this, we cannot
153 #define HANDLE_INST(NUM, OPCODE, CLASS) \
154 RetTy visit##OPCODE(CLASS &I) { DELEGATE(CLASS); }
|
| /packages/apps/Stk/src/com/android/stk/ |
| StkCmdReceiver.java | 61 args.putInt(StkAppService.OPCODE, op);
94 args.putInt(StkAppService.OPCODE, StkAppService.OP_LOCALE_CHANGED);
101 args.putInt(StkAppService.OPCODE, StkAppService.OP_IDLE_SCREEN);
|
| BootCompletedReceiver.java | 45 args.putInt(StkAppService.OPCODE, StkAppService.OP_BOOT_COMPLETED);
|
| /external/llvm/include/llvm/IR/ |
| InstVisitor.h | 27 #define HANDLE_INST(NUM, OPCODE, CLASS) class CLASS;
79 /// opcode.
122 #define HANDLE_INST(NUM, OPCODE, CLASS) \
123 case Instruction::OPCODE: return \
125 visit##OPCODE(static_cast<CLASS&>(I));
150 // These functions can also implement fan-out, when a single opcode and
154 #define HANDLE_INST(NUM, OPCODE, CLASS) \
155 RetTy visit##OPCODE(CLASS &I) { \
|
| /toolchain/binutils/binutils-2.25/include/opcode/ |
| spu.h | 72 #define APUOP(TAG,MACFORMAT,OPCODE,MNEMONIC,ASMFORMAT,DEP,PIPE) \
74 #define APUOPFB(TAG,MACFORMAT,OPCODE,FB,MNEMONIC,ASMFORMAT,DEP,PIPE) \
76 #include "opcode/spu-insns.h"
85 unsigned int opcode; member in struct:spu_opcode
|
| h8300.h | 0 /* Opcode table for the H8/300
617 #define EXPAND2_STD_IMM(CODE, WEIGHT, NAME, SRC, PREFIX, OPCODE, IGN, IMMLIST) \
618 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTINC, E}}, {{PREFIX, TO_POSTINC, OPCODE, IGN, IMMLIST, E}}}, \
619 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPOSTDEC, E}}, {{PREFIX, TO_POSTDEC, OPCODE, IGN, IMMLIST, E}}}, \
620 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREINC, E}}, {{PREFIX, TO_PREINC, OPCODE, IGN, IMMLIST, E}}}, \
621 {CODE, AV_H8SX, 0, NAME, {{SRC, RDPREDEC, E}}, {{PREFIX, TO_PREDEC, OPCODE, IGN, IMMLIST, E}}}, \
622 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP2DST, E}}, {{PREFIX, TO_DISP2, OPCODE, IGN, IMMLIST, E}}}, \
623 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP16DST, E}}, {{PREFIX, TO_DISP16, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}}, \
624 {CODE, AV_H8SX, 0, NAME, {{SRC, DISP32DST, E}}, {{PREFIX, TO_DISP32, OPCODE, IGN, DSTDISP32LIST, IMMLIST, E}}}, \
625 {CODE, AV_H8SX, 0, NAME, {{SRC, INDEXB16D, E}}, {{PREFIX, TO_DISP16B, OPCODE, IGN, DSTDISP16LIST, IMMLIST, E}}},
[all...] |
| /toolchain/binutils/binutils-2.25/gas/config/ |
| tc-rl78.c | 466 so that we can retain this alignment as we adjust opcode sizes. */
544 0 /* opcode */);
693 opcode (like BRA.S). We store the number of total bytes we need in
695 existing opcode bytes to figure out what actual opcode we need to
728 /* Given the opcode bytes at OP, figure out which opcode it is and
729 return the type of opcode. We use this to re-encode the opcode as
805 /* Estimate how big the opcode is after this relax pass. The retur
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
50 // The opcode that should be used to compare Op0 and Op1.
51 unsigned Opcode;
56 // The mask of CC values that Opcode can produce.
271 for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
272 if (getOperationAction(Opcode, VT) == Legal)
273 setOperationAction(Opcode, VT, Expand);
[all...] |
