| /external/mesa3d/src/gallium/drivers/nv50/codegen/ |
| nv50_ir_target_nv50.cpp | 102 { OP_LG2, 0x1, 0x1, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
492 case OP_LG2:
|
| nv50_ir.h | 82 OP_LG2,
|
| nv50_ir_peephole.cpp | 532 case OP_LG2: res.data.f32 = log2f(imm.reg.data.f32); break;
809 case OP_LG2:
[all...] |
| nv50_ir_lowering_nv50.cpp | 976 bld.mkOp1(OP_LG2, TYPE_F32, val, i->getSrc(0));
|
| nv50_ir_emit_nv50.cpp | [all...] |
| nv50_ir_from_sm4.cpp | 401 case SM4_OPCODE_LOG: return OP_LG2;
[all...] |
| nv50_ir_from_tgsi.cpp | [all...] |
| /external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
| nv50_ir_target_nvc0.cpp | 241 { OP_LG2, 0x1, 0x1, 0x0, 0x8, 0x0, 0x0 },
603 case OP_LG2:
|
| nv50_ir_lowering_nvc0.cpp | 976 bld.mkOp1(OP_LG2, TYPE_F32, val, i->getSrc(0));
[all...] |
| nv50_ir_emit_nvc0.cpp | [all...] |
