| /external/google-breakpad/src/third_party/libdisasm/ |
| ia32_implicit.c | 23 {{ OP_R | OP_W, REG_BYTE_OFFSET }, {0}}; /* aaa */
28 {{ OP_R | OP_W, REG_WORD_OFFSET }, {0}}; /* aad */
33 {{ OP_R | OP_W, REG_EIP_INDEX },
34 { OP_R | OP_W, REG_ESP_INDEX }, {0}}; /* call, ret */
38 {{ OP_R | OP_W, REG_WORD_OFFSET },
43 {{ OP_R | OP_W, REG_DWORD_OFFSET },
48 {{ OP_R | OP_W, REG_CTRL_OFFSET}, {0}}; /* clts */
52 {{ OP_R | OP_W, REG_BYTE_OFFSET }, {0}}; /* cmpxchg */
56 {{ OP_R | OP_W, REG_DWORD_OFFSET }, {0}}; /* cmpxchg */
60 {{ OP_R | OP_W, REG_DWORD_OFFSET },
[all...] |
| ia32_opcode_tables.c | 8 { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add", "", 0, 0, 0, INS_SET_ALL, 0 },
9 { 0, INS_ADD, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add", "", 0, 0, 0, INS_SET_ALL, 0 },
10 { 0, INS_ADD, 0, ADDRMETH_G | OPTYPE_b | OP_W | OP_R, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add", "", 0, 0, 0, INS_SET_ALL, 0 },
11 { 0, INS_ADD, 0, ADDRMETH_G | OPTYPE_v | OP_W | OP_R, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add", "", 0, 0, 0, INS_SET_ALL, 0 },
12 { 0, INS_ADD, 0, ADDRMETH_RR | OPTYPE_b | OP_W | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add", "", 0, 0, 0, INS_SET_ALL, 0 },
13 { 0, INS_ADD, 0, ADDRMETH_RR | OPTYPE_v | OP_W | OP_R, ADDRMETH_I | OPTYPE_v | OP_SIGNED | OP_R, ARG_NONE, cpu_80386 | isa_GP, "add", "", 0, 0, 0, INS_SET_ALL, 0 },
15 { 0, INS_POP, 0, ADDRMETH_RS | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386 | isa_GP, "pop", "", 0, 0, 0, 0 , 33 },
16 { 0, INS_OR, 0, ADDRMETH_E | OPTYPE_b | OP_W | OP_R, ADDRMETH_G | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or", "", 0, 0, 0, INS_SET_ALL, 0 },
17 { 0, INS_OR, 0, ADDRMETH_E | OPTYPE_v | OP_W | OP_R, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or", "", 0, 0, 0, INS_SET_ALL, 0 },
18 { 0, INS_OR, 0, ADDRMETH_G | OPTYPE_b | OP_W | OP_R, ADDRMETH_E | OPTYPE_b | OP_R, ARG_NONE, cpu_80386 | isa_GP, "or", "", 0, 0, (…)
[all...] |
| ia32_insn.h | 235 #define OP_W 0x002 /* operand is WRITTEN */
236 #define OP_RW 0x003 /* (OP_R|OP_W): convenience macro */
|
| /external/lzma/Asm/x86/ |
| AesOpt.asm | 55 OP_W macro op, op2
69 OP_W op, xmm7
101 OP_W movdqa, [rD + i * 16]
104 OP_W CBC_DEC_UPDATE, i * 16
211 OP_W XOR_UPD_1, i * 16
212 OP_W XOR_UPD_2, i * 16
|
