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    Searched refs:OffsetOp (Results 1 - 9 of 9) sorted by null

  /external/llvm/lib/Target/Lanai/InstPrinter/
LanaiInstPrinter.cpp 224 const MCOperand &OffsetOp,
226 assert((OffsetOp.isImm() || OffsetOp.isExpr()) && "Immediate expected");
227 if (OffsetOp.isImm()) {
228 assert(isInt<SizeInBits>(OffsetOp.getImm()) && "Constant value truncated");
229 OS << OffsetOp.getImm();
231 OffsetOp.getExpr()->print(OS, &MAI);
238 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
243 printMemoryImmediateOffset<16>(MAI, OffsetOp, OS);
253 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1)
    [all...]
  /external/llvm/lib/Target/BPF/InstPrinter/
BPFInstPrinter.cpp 69 const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
71 if (OffsetOp.isImm())
72 O << formatDec(OffsetOp.getImm());
  /external/llvm/lib/Target/WebAssembly/
WebAssemblyRegisterInfo.cpp 112 unsigned OffsetOp = MRI.createVirtualRegister(PtrRC);
114 OffsetOp)
120 .addReg(OffsetOp);
  /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
SIMCCodeEmitter.cpp 201 const MCOperand &OffsetOp = MI.getOperand(OpNo + 1);
204 assert(OffsetOp.isImm());
207 (getMachineOpValue(MI, OffsetOp, Fixup) & SMRD_OFFSET_MASK)
  /external/llvm/lib/Target/AMDGPU/
SIRegisterInfo.cpp 329 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset);
330 int64_t NewOffset = OffsetOp->getImm() + Offset;
334 OffsetOp->setImm(NewOffset);
    [all...]
  /external/llvm/lib/Target/Hexagon/
HexagonOptAddrMode.cpp 143 const MachineOperand &OffsetOp = MI->getOperand(3);
144 if (!OffsetOp.isImm() || OffsetOp.getImm() > 3)
  /external/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp     [all...]
  /external/llvm/lib/CodeGen/SelectionDAG/
SelectionDAG.cpp     [all...]
  /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/
SelectionDAG.cpp     [all...]

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