| /external/v8/tools/clang/rewrite_to_chrome_style/tests/ |
| operators-expected.cc | 11 struct Op2 {};
13 inline bool operator==(const Op2&, const Op2) {
23 blink::Op2 a2, b2;
|
| operators-original.cc | 11 struct Op2 {};
13 inline bool operator==(const Op2&, const Op2) {
23 blink::Op2 a2, b2;
|
| /external/llvm/lib/Target/Lanai/MCTargetDesc/ |
| LanaiMCCodeEmitter.cpp | 145 const MCOperand Op2 = Inst.getOperand(2);
148 ((Op2.isImm() && Op2.getImm() != 0) ||
149 (Op2.isReg() && Op2.getReg() != Lanai::R0) || (Op2.isExpr())))
156 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) ||
157 (Op2.isReg() && Op2.getReg() != Lanai::R0))
[all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 85 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
93 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
99 Ops[5].getAsInteger(10, Op2);
100 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
111 uint32_t Op2 = Bits & 0x7;
114 utostr(CRm) + "_" + utostr(Op2);
|
| /system/core/libpixelflinger/codeflinger/ |
| ARMAssemblerInterface.h | 125 uint32_t Op2) = 0;
225 ADC(int cc, int s, int Rd, int Rn, uint32_t Op2) {
226 dataProcessing(opADC, cc, s, Rd, Rn, Op2);
229 ADD(int cc, int s, int Rd, int Rn, uint32_t Op2) {
230 dataProcessing(opADD, cc, s, Rd, Rn, Op2);
233 AND(int cc, int s, int Rd, int Rn, uint32_t Op2) {
234 dataProcessing(opAND, cc, s, Rd, Rn, Op2);
237 BIC(int cc, int s, int Rd, int Rn, uint32_t Op2) {
238 dataProcessing(opBIC, cc, s, Rd, Rn, Op2);
241 EOR(int cc, int s, int Rd, int Rn, uint32_t Op2) {
[all...] |
| ARMAssemblerInterface.cpp | 80 int Rd, int Rn, uint32_t Op2)
82 dataProcessing(opADD, cc, s, Rd, Rn, Op2);
85 int Rd, int Rn, uint32_t Op2)
87 dataProcessing(opSUB, cc, s, Rd, Rn, Op2);
|
| Arm64Assembler.cpp | 340 int s, int Rd, int Rn, uint32_t Op2)
355 if(Op2 == OPERAND_REG_IMM && mAddrMode.reg_imm_shift > 31)
363 if(Op2 == OPERAND_IMM)
368 Op2 = mTmpReg2;
377 if(Op2 == OPERAND_REG_IMM)
383 else if(Op2 < OPERAND_REG)
387 Rm = Op2;
408 int s, int Rd, int Rn, uint32_t Op2)
419 dataProcessingCommon(opcode, s, Wd, Rn, Op2);
423 dataProcessingCommon(opSUB, 1, mTmpReg3, Rn, Op2);
[all...] |
| MIPS64Assembler.cpp | 395 int s, int Rd, int Rn, uint32_t Op2)
410 if (dataProcAdrModes(Op2, src) == SRC_REG) {
419 if (dataProcAdrModes(Op2, src, true) == SRC_REG) {
428 if (dataProcAdrModes(Op2, src, true) == SRC_REG) {
437 if (dataProcAdrModes(Op2, src, true) == SRC_REG) {
446 if (dataProcAdrModes(Op2, src, true) == SRC_REG) {
454 if (dataProcAdrModes(Op2, src) == SRC_REG) {
462 if (dataProcAdrModes(Op2, src) == SRC_REG) {
470 if (dataProcAdrModes(Op2, src) == SRC_IMM) {
480 if (dataProcAdrModes(Op2, src) == SRC_IMM)
[all...] |
| ARMAssemblerProxy.cpp | 161 int Rd, int Rn, uint32_t Op2)
163 mTarget->dataProcessing(opcode, cc, s, Rd, Rn, Op2);
303 void ARMAssemblerProxy::ADDR_ADD(int cc, int s, int Rd, int Rn, uint32_t Op2){
304 mTarget->ADDR_ADD(cc, s, Rd, Rn, Op2);
306 void ARMAssemblerProxy::ADDR_SUB(int cc, int s, int Rd, int Rn, uint32_t Op2){
307 mTarget->ADDR_SUB(cc, s, Rd, Rn, Op2);
|
| /external/swiftshader/third_party/LLVM/include/llvm/Target/ |
| TargetSelectionDAGInfo.h | 59 SDValue Op1, SDValue Op2,
76 SDValue Op1, SDValue Op2,
92 SDValue Op1, SDValue Op2,
|
| /external/llvm/lib/Target/XCore/Disassembler/ |
| XCoreDisassembler.cpp | 241 Decode2OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2) {
254 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 0, 2);
259 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2,
269 Op2 = (Op2High << 2) | fieldFromInstruction(Insn, 2, 2);
347 unsigned Op1, Op2;
348 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
353 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
360 unsigned Op1, Op2;
361 DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
366 DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder)
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreSelectionDAGInfo.h | 26 SDValue Chain, SDValue Op1, SDValue Op2,
|
| /device/linaro/bootloader/edk2/MdeModulePkg/Universal/EbcDxe/ |
| EbcExecute.c | 42 IN UINT64 Op2
877 @param Op2 Operand 2 from the instruction
879 @return ~Op2
886 IN UINT64 Op2
897 @param Op2 Operand 2 from the instruction
899 @return Op2 * -1
906 IN UINT64 Op2
917 @param Op2 Operand 2 from the instruction
919 @return Op1 + Op2
926 IN UINT64 Op2
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGTargetInfo.h | 51 SDValue Op2, SDValue Op3,
67 SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile,
80 SDValue Op2, SDValue Op3,
92 SDValue Op1, SDValue Op2, SDValue Op3,
129 SDValue Op1, SDValue Op2,
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/ |
| PTXSelectionDAGInfo.h | 44 SDValue Op1, SDValue Op2,
|
| /external/llvm/lib/Target/Lanai/ |
| LanaiMemAluCombiner.cpp | 170 bool isSameOperand(const MachineOperand &Op1, const MachineOperand &Op2) {
171 if (Op1.getType() != Op2.getType())
176 return Op1.getReg() == Op2.getReg();
178 return Op1.getImm() == Op2.getImm();
295 MachineOperand &Op2 = AluIter->getOperand(2);
302 if (Op2.isImm()) {
313 // Check that the Op2 would fit in the immediate field of the
315 ((IsSpls && isInt<10>(Op2.getImm())) ||
316 (!IsSpls && isInt<16>(Op2.getImm())))) ||
317 Offset.getImm() == Op2.getImm())
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 60 SDValue Op1, SDValue Op2,
|
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCCodeEmitter.cpp | 162 MCOperand Op2 = MI.getOperand(2);
163 assert(Op2.isImm() && "Second operand is not immediate.");
164 Encoding |= Op2.getImm() & 0xffff;
|
| /external/swiftshader/third_party/LLVM/lib/Target/PTX/InstPrinter/ |
| PTXInstPrinter.cpp | 143 const MCOperand &Op2 = MI->getOperand(OpNo+1);
145 if (Op2.getImm() == 0)
147 O << "+" << Op2.getImm();
|
| /external/swiftshader/third_party/LLVM/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 816 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
817 if (Op.isReg() && Op.getReg() == X86::DX && isDstOp(Op2)) {
821 delete &Op2;
829 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
830 if (isSrcOp(Op) && Op2.isReg() && Op2.getReg() == X86::DX) {
834 delete &Op2;
843 X86Operand &Op2 = *(X86Operand*)Operands.begin()[2];
844 if (isSrcOp(Op) && isDstOp(Op2)) {
848 delete &Op2;
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMSelectionDAGInfo.h | 57 SDValue Chain, SDValue Op1, SDValue Op2,
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| SelectionDAG.h | 484 SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2,
490 Ops.push_back(Op2);
708 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2);
709 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
711 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
713 SDNode *UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2,
725 SDValue Op1, SDValue Op2);
727 SDValue Op1, SDValue Op2, SDValue Op3);
[all...] |
| ISDOpcodes.h | [all...] |
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| LegalizeVectorOps.cpp | 273 SDValue Op2 = Op.getOperand(2);
288 Op2 = DAG.getNode(ISD::BITCAST, DL, VT, Op2);
295 Op2 = DAG.getNode(ISD::AND, DL, VT, Op2, NotMask);
296 return DAG.getNode(ISD::OR, DL, VT, Op1, Op2);
|
| /external/llvm/lib/IR/ |
| ProfileSummary.cpp | 134 ConstantAsMetadata *Op2 =
137 if (!Op0 || !Op1 || !Op2)
141 cast<ConstantInt>(Op2->getValue())->getZExtValue());
|
