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    Searched refs:PCI_BASE_ADDRESSREG_OFFSET (Results 1 - 9 of 9) sorted by null

  /device/linaro/bootloader/edk2/MdeModulePkg/Bus/Pci/UfsPciHcPei/
UfsPciHcPei.c 126 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), 0xFFFFFFFF);
127 Size = PciRead32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET));
132 PciWrite32 (PCI_LIB_ADDRESS (Bus, Device, Function, PCI_BASE_ADDRESSREG_OFFSET), (UINT32)(PcdGet32 (PcdUfsPciHostControllerMmioBase) + Size * Private->TotalUfsHcs));
  /device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb/
DebugCommunicationLibUsb.c 537 EhciMemoryBase = 0xFFFFFC00 & PciRead32(PcdGet32(PcdUsbEhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET);
543 UsbDebugPortMemoryBase = 0xFFFFFC00 & PciRead32(PcdGet32(PcdUsbEhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + Handle->DebugPortBarNumber * 4);
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  /device/linaro/bootloader/edk2/SourceLevelDebugPkg/Library/DebugCommunicationLibUsb3/
DebugCommunicationLibUsb3Common.c 169 Low = PciRead32 (PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET);
170 High = PciRead32 (PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + 4);
176 PciWrite32(PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET, XhciMmioBase & 0xFFFFFFFF);
177 PciWrite32(PcdGet32(PcdUsbXhciPciAddress) + PCI_BASE_ADDRESSREG_OFFSET + 4, (RShiftU64 (XhciMmioBase, 32) & 0xFFFFFFFF));
  /device/linaro/bootloader/edk2/MdeModulePkg/Library/BaseSerialPortLib16550/
BaseSerialPortLib16550.c 309 SerialRegisterBase = PciRead32 (PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4);
338 PciLibAddress + PCI_BASE_ADDRESSREG_OFFSET + BarIndex * 4,
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  /device/linaro/bootloader/edk2/BaseTools/Source/C/Include/IndustryStandard/
pci22.h 301 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
  /device/linaro/bootloader/edk2/EdkCompatibilityPkg/Foundation/Include/IndustryStandard/
pci22.h 313 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
  /device/linaro/bootloader/edk2/MdePkg/Include/IndustryStandard/
Pci22.h 536 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
  /external/syslinux/gpxe/src/include/gpxe/efi/IndustryStandard/
Pci22.h 340 #define PCI_BASE_ADDRESSREG_OFFSET 0x10
  /device/linaro/bootloader/edk2/QuarkPlatformPkg/Platform/Pei/PlatformInit/
MrcWrapper.c 70 RegData32 = PciRead32 (PCI_LIB_ADDRESS(IohUartBus, IohUartDev, UartIdx, PCI_BASE_ADDRESSREG_OFFSET));
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