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    Searched refs:PREDICATE_BIT (Results 1 - 9 of 9) sorted by null

  /external/mesa3d/src/gallium/drivers/radeon/
R600RegisterInfo.cpp 40 Reserved.set(AMDGPU::PREDICATE_BIT);
79 case AMDGPU::PREDICATE_BIT:
98 case AMDGPU::PREDICATE_BIT:
R600InstrInfo.cpp 62 .addReg(0) // PREDICATE_BIT
74 .addReg(0); // PREDICATE_BIT
85 MachineInstrBuilder(MI).addReg(0); // PREDICATE_BIT
281 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
291 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
354 case AMDGPU::PREDICATE_BIT:
463 MachineInstrBuilder(MI).addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
R600GenRegisterInfo.pl 72 def PREDICATE_BIT : R600Reg<"PredicateBit">;
95 PREDICATE_BIT)>;
R600ISelLowering.cpp 208 .addReg(AMDGPU::PREDICATE_BIT)
215 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
222 .addReg(AMDGPU::PREDICATE_BIT)
229 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
  /external/llvm/lib/Target/AMDGPU/
R600RegisterInfo.cpp 43 Reserved.set(AMDGPU::PREDICATE_BIT);
R600InstrInfo.cpp 788 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
803 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
882 case AMDGPU::PREDICATE_BIT:
1009 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
1017 MIB.addReg(AMDGPU::PREDICATE_BIT, RegState::Implicit);
    [all...]
R600ISelLowering.cpp 534 AMDGPU::PREDICATE_BIT)
541 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
548 AMDGPU::PREDICATE_BIT)
555 .addReg(AMDGPU::PREDICATE_BIT, RegState::Kill);
    [all...]
AMDILCFGStructurizer.cpp     [all...]
  /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/
R600MCCodeEmitter.cpp 301 if (MO.isReg() && MO.getReg() != AMDGPU::PREDICATE_BIT) {
584 case AMDGPU::PREDICATE_BIT:
602 case AMDGPU::PREDICATE_BIT:

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