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Searched
refs:ProcIndices
(Results
1 - 3
of
3
) sorted by null
/external/llvm/utils/TableGen/
CodeGenSchedule.cpp
503
SchedClasses.back().
ProcIndices
.push_back(0);
514
IdxVec
ProcIndices
(1, 0);
516
unsigned SCIdx = addSchedClass(ItinDef, Writes, Reads,
ProcIndices
);
541
if (SC.
ProcIndices
[0] != 0)
545
IdxVec
ProcIndices
;
547
ProcIndices
.push_back(0);
552
ProcIndices
.push_back(0);
565
ProcIndices
.push_back(ProcModel.Index);
579
if (!std::count(
ProcIndices
.begin(),
ProcIndices
.end(), PI->Index)
[
all
...]
CodeGenSchedule.h
99
IdxVec
ProcIndices
;
109
/// Writes and ReadDefs are empty.
ProcIndices
contains 0 for any processor.
113
/// subtargets.
ProcIndices
contains 0 for any processor.
117
/// instructions to this class.
ProcIndices
contains all the processors that
122
/// resolved at runtime.
ProcIndices
contains the set of processors that may
123
/// require the class.
ProcIndices
are propagated through SchedClasses as
135
IdxVec
ProcIndices
;
378
ArrayRef<unsigned>
ProcIndices
);
418
unsigned FromClassIdx, ArrayRef<unsigned>
ProcIndices
);
430
ArrayRef<unsigned>
ProcIndices
);
[
all
...]
SubtargetEmitter.cpp
826
if (TI->
ProcIndices
[0] == 0) {
830
IdxIter PIPos = std::find(TI->
ProcIndices
.begin(),
831
TI->
ProcIndices
.end(), ProcModel.Index);
832
if (PIPos != TI->
ProcIndices
.end()) {
844
// If
ProcIndices
contains 0, this class applies to all processors.
845
assert(!SC.
ProcIndices
.empty() && "expect at least one procidx");
846
if (SC.
ProcIndices
[0] != 0) {
847
IdxIter PIPos = std::find(SC.
ProcIndices
.begin(),
848
SC.
ProcIndices
.end(), ProcModel.Index);
849
if (PIPos == SC.
ProcIndices
.end()
[
all
...]
Completed in 311 milliseconds