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    Searched refs:RC_MASK_XYZW (Results 1 - 19 of 19) sorted by null

  /external/mesa3d/src/gallium/drivers/r300/compiler/
r3xx_fragprog.c 44 callback(data, c->OutputColor[0], RC_MASK_XYZW);
45 callback(data, c->OutputColor[1], RC_MASK_XYZW);
46 callback(data, c->OutputColor[2], RC_MASK_XYZW);
47 callback(data, c->OutputColor[3], RC_MASK_XYZW);
radeon_rename_regs.c 80 RC_MASK_XYZW);
radeon_dataflow_swizzles.c 69 phase_refmask &= RC_MASK_XYZW;
75 mov->U.I.SrcReg[0].Negate = RC_MASK_XYZW;
radeon_program.c 160 RC_MASK_XYZW);
176 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
radeon_opcodes.c 533 srcmasks[0] |= RC_MASK_XYZW;
561 srcmasks[0] |= RC_MASK_XYZW;
562 srcmasks[1] |= RC_MASK_XYZW;
566 srcmasks[1] |= RC_MASK_XYZW;
radeon_pair_regalloc.c 293 writemask = RC_MASK_XYZW;
321 * then the writemask will be set to RC_MASK_XYZW
410 return reg / RC_MASK_XYZW;
415 return (reg % RC_MASK_XYZW) + 1;
424 return (index * RC_MASK_XYZW) + (writemask - 1);
446 for(a_mask = 1; a_mask <= RC_MASK_XYZW; a_mask++) {
447 for (b_mask = a_mask + 1; b_mask <= RC_MASK_XYZW;
550 regs = ra_alloc_reg_set(NULL, s->C->max_temp_regs * RC_MASK_XYZW);
radeon_emulate_branches.c 168 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW;
187 inst_cmp->U.I.DstReg.WriteMask = RC_MASK_XYZW;
190 inst_cmp->U.I.SrcReg[0].Negate = RC_MASK_XYZW;
298 inst_mov->U.I.DstReg.WriteMask = RC_MASK_XYZW;
radeon_program_constants.h 153 #define RC_MASK_XYZW (RC_MASK_X|RC_MASK_Y|RC_MASK_Z|RC_MASK_W)
r3xx_vertprog.c 55 return mask & RC_MASK_XYZW;
170 src->Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
252 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
259 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
266 vpi->SrcReg[0].Negate ? RC_MASK_XYZW : RC_MASK_NONE) |
686 new_inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
755 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
774 callback(data, i, RC_MASK_XYZW);
radeon_program_tex.c 173 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
230 inst_add->U.I.SrcReg[1].Negate = inst_add->U.I.SrcReg[1].Negate ^ RC_MASK_XYZW;
232 inst_add->U.I.SrcReg[0].Negate = inst_add->U.I.SrcReg[0].Negate ^ RC_MASK_XYZW;
464 inst_mad->U.I.SrcReg[2].Negate = RC_MASK_XYZW;
481 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
489 (!c->is_r500 && inst->U.I.DstReg.WriteMask != RC_MASK_XYZW))) {
501 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
radeon_optimize.c 115 sc_data->ReaderData->AbortOnRead = RC_MASK_XYZW;
119 sc_data->ReaderData->AbortOnRead = RC_MASK_XYZW;
226 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW;
240 inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
261 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW;
274 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW;
radeon_program_alu.c 159 newreg.Negate = newreg.Negate ^ RC_MASK_XYZW;
370 if (inst->U.I.DstReg.WriteMask != RC_MASK_XYZW || inst->U.I.DstReg.File != RC_FILE_TEMPORARY) {
379 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
701 inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
766 dst.WriteMask = RC_MASK_XYZW;
839 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW;
840 inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
848 inst->U.I.SrcReg[0].Negate ^= RC_MASK_XYZW;
849 inst->U.I.SrcReg[1].Negate ^= RC_MASK_XYZW;
    [all...]
radeon_program_print.c 164 if (dst.WriteMask != RC_MASK_XYZW) {
235 int trivial_negate = (src.Negate == RC_MASK_NONE || src.Negate == RC_MASK_XYZW);
237 if (src.Negate == RC_MASK_XYZW)
radeon_dataflow_deadcode.c 195 refmask &= RC_MASK_XYZW;
radeon_compiler.c 341 inst_add->U.I.SrcReg[1].Negate = RC_MASK_XYZW;
radeon_compiler_util.c 46 mask &= RC_MASK_XYZW;
radeon_dataflow.c 51 refmask &= RC_MASK_XYZW;
  /external/mesa3d/src/gallium/drivers/r300/compiler/tests/
rc_test_helpers.c 119 src_reg->Negate = RC_MASK_XYZW;
260 inst->U.I.DstReg.WriteMask = RC_MASK_XYZW;
  /external/mesa3d/src/gallium/drivers/r300/
r300_tgsi_to_rc.c 215 dst->Negate = src->Register.Negate ? RC_MASK_XYZW : 0;

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