/external/llvm/lib/Target/SystemZ/ |
SystemZSelectionDAGInfo.cpp | 178 SDValue ROTL = DAG.getNode(ISD::ROTL, DL, MVT::i32, SRL, 180 return ROTL;
|
SystemZISelDAGToDAG.cpp | 109 // (or (rotl Input, Rotate), ~Mask) 113 // (and (rotl Input, Rotate), Mask) 807 case ISD::ROTL: { 859 // Treat (shl X, count) as (rotl X, size-count) as long as the bottom 864 // Treat (shl X, count) as (and (rotl X, count), ~0<<count). 886 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top 891 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count), [all...] |
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
ISDOpcodes.h | 317 SHL, SRA, SRL, ROTL, ROTR, [all...] |
/external/boringssl/src/decrepit/cast/ |
cast.c | 85 #define ROTL(a, n) (_lrotl(a, n)) 87 #define ROTL(a, n) ((((a) << (n)) | ((a) >> ((-(n))&31))) & 0xffffffffL) 94 t = ROTL(t, (key[n * 2 + 1])); \
|
/external/llvm/include/llvm/CodeGen/ |
ISDOpcodes.h | 339 SHL, SRA, SRL, ROTL, ROTR, [all...] |
/external/mesa3d/src/gallium/drivers/radeon/ |
R600ISelLowering.cpp | 43 setOperationAction(ISD::ROTL, MVT::i32, Custom); 250 case ISD::ROTL: return LowerROTL(Op, DAG);
|
/external/avb/libavb/ |
avb_sha256.c | 42 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
|
avb_sha512.c | 42 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
|
/external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
LegalizeVectorOps.cpp | 157 case ISD::ROTL:
|
DAGCombiner.cpp | [all...] |
/external/vboot_reference/firmware/2lib/ |
2sha256.c | 44 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
|
2sha512.c | 44 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
|
/external/vboot_reference/firmware/lib/cryptolib/ |
sha256.c | 45 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
|
sha512.c | 45 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n)))
|
/toolchain/binutils/binutils-2.25/gas/config/ |
rx-parse.y | 162 %token RACW REIT REVL REVW RMPA ROLC RORC ROTL ROTR ROUND RTE RTFI RTS RTSD 734 | ROTL { sub_op = 6; } op_shift_rot 752 | ROTL '#' EXPR ',' REG 870 /* 000:SHLR, 001:SHAR, 010:SHLL, 011:-, 100:ROTR, 101:REVW, 110:ROTL, 111:REVL */ 1071 OPC(ROTL), [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
PPCISelDAGToDAG.cpp | 358 } else if (Opcode == ISD::ROTL) { [all...] |
/external/llvm/lib/Target/X86/ |
X86IntrinsicsInfo.h | [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
SPUISelLowering.cpp | 239 setOperationAction(ISD::ROTL, MVT::i32, Legal); 240 setOperationAction(ISD::ROTL, MVT::i16, Legal); 241 setOperationAction(ISD::ROTL, MVT::i8, Custom); [all...] |
/external/llvm/lib/Target/NVPTX/ |
NVPTXISelLowering.cpp | 175 setOperationAction(ISD::ROTL, MVT::i64, Legal); 178 setOperationAction(ISD::ROTL, MVT::i64, Expand); 182 setOperationAction(ISD::ROTL, MVT::i32, Legal); 185 setOperationAction(ISD::ROTL, MVT::i32, Expand); 189 setOperationAction(ISD::ROTL, MVT::i16, Expand); 191 setOperationAction(ISD::ROTL, MVT::i8, Expand); [all...] |
/external/llvm/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 97 setOperationAction(ISD::ROTL, MVT::i8, Expand); 99 setOperationAction(ISD::ROTL, MVT::i16, Expand); [all...] |
/external/swiftshader/third_party/LLVM/lib/Target/MSP430/ |
MSP430ISelLowering.cpp | 104 setOperationAction(ISD::ROTL, MVT::i8, Expand); 106 setOperationAction(ISD::ROTL, MVT::i16, Expand); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
SelectionDAGDumper.cpp | 194 case ISD::ROTL: return "rotl";
|
LegalizeVectorOps.cpp | 282 case ISD::ROTL: [all...] |
/external/llvm/lib/Target/BPF/ |
BPFISelLowering.cpp | 96 setOperationAction(ISD::ROTL, MVT::i64, Expand);
|
/external/mmc-utils/3rdparty/hmac_sha/ |
sha2.c | 48 #define ROTL(x, n) ((x << n) | (x >> ((sizeof(x) << 3) - n))) [all...] |