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    Searched refs:ReservedRegs (Results 1 - 9 of 9) sorted by null

  /external/mesa3d/src/gallium/drivers/radeon/
R600MachineFunctionInfo.h 27 std::vector<unsigned> ReservedRegs;
R600RegisterInfo.cpp 50 for (std::vector<unsigned>::const_iterator I = MFI->ReservedRegs.begin(),
51 E = MFI->ReservedRegs.end(); I != E; ++I) {
R600ISelLowering.cpp 151 MFI->ReservedRegs.push_back(ReservedReg);
  /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
RegisterScavenging.h 62 /// ReservedRegs - A bitvector of reserved registers.
64 BitVector ReservedRegs;
129 bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); }
  /external/swiftshader/third_party/LLVM/lib/CodeGen/
DeadMachineInstructionElim.cpp 92 BitVector ReservedRegs = TRI->getReservedRegs(MF);
102 LivePhysRegs = ReservedRegs;
RegisterScavenging.cpp 63 RegsAvailable ^= ReservedRegs;
95 ReservedRegs = TRI->getReservedRegs(MF);
235 used = ~RegsAvailable & ~ReservedRegs;
PostRASchedulerList.cpp 441 BitVector ReservedRegs = TRI->getReservedRegs(MF);
482 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
518 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
  /external/llvm/include/llvm/CodeGen/
MachineRegisterInfo.h 101 /// ReservedRegs - This is a bit vector of reserved registers. The target
105 BitVector ReservedRegs;
746 return !ReservedRegs.empty();
753 return !reservedRegsFrozen() || ReservedRegs.test(PhysReg);
763 return ReservedRegs;
    [all...]
  /external/llvm/lib/CodeGen/
MachineRegisterInfo.cpp 442 ReservedRegs = getTargetRegisterInfo()->getReservedRegs(MF);
443 assert(ReservedRegs.size() == getTargetRegisterInfo()->getNumRegs() &&
444 "Invalid ReservedRegs vector from target");

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