| /prebuilts/go/darwin-x86/src/crypto/rc4/ |
| rc4_arm.s | 20 #define Rt2 R12
43 MOVBU Rj<<2(Rstate), Rt2
44 MOVB Rt2, Ri<<2(Rstate)
48 ADD Rt2, Rt
51 MOVBU Rk<<0(Rsrc), Rt2
52 EOR Rt, Rt2
53 MOVB Rt2, Rk<<0(Rdst)
|
| /prebuilts/go/linux-x86/src/crypto/rc4/ |
| rc4_arm.s | 20 #define Rt2 R12
43 MOVBU Rj<<2(Rstate), Rt2
44 MOVB Rt2, Ri<<2(Rstate)
48 ADD Rt2, Rt
51 MOVBU Rk<<0(Rsrc), Rt2
52 EOR Rt, Rt2
53 MOVB Rt2, Rk<<0(Rdst)
|
| /prebuilts/go/darwin-x86/src/crypto/sha1/ |
| sha1block_arm.s | 37 #define Rt2 R11 // Temporary
59 MOVBU 1(Rdata), Rt2 ; \
62 ORR Rt2<<16, Rt0, Rt0 ; \
73 MOVW (-8*4)(Rw), Rt2 ; \
76 EOR Rt2, Rt0, Rt0 ; \
202 MOVM.IB (R13), [Rt0,Rt1,Rt2,Rctr,Rw]
205 ADD Rt2, Rc
|
| /prebuilts/go/linux-x86/src/crypto/sha1/ |
| sha1block_arm.s | 37 #define Rt2 R11 // Temporary
59 MOVBU 1(Rdata), Rt2 ; \
62 ORR Rt2<<16, Rt0, Rt0 ; \
73 MOVW (-8*4)(Rw), Rt2 ; \
76 EOR Rt2, Rt0, Rt0 ; \
202 MOVM.IB (R13), [Rt0,Rt1,Rt2,Rctr,Rw]
205 ADD Rt2, Rc
|
| /external/llvm/test/MC/AArch64/ |
| arm64-diags.s | 155 ; Load pair instructions where Rt==Rt2 and writeback load/store instructions
156 ; where Rt==Rn or Rt2==Rn are unpredicatable.
194 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
197 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
200 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
203 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
206 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
209 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
212 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==Rt
215 ; CHECK-ERRORS: error: unpredictable LDP instruction, Rt2==R
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | [all...] |
| /device/linaro/bootloader/edk2/ArmPkg/Library/ArmDisassemblerLib/ |
| ThumbDisassembler.c | 268 { "MRRC", 0xec500000, 0xfff00000, MRRC_THUMB2 }, // MRRC <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
269 { "MRRC2", 0xfc500000, 0xfff00000, MRRC_THUMB2 }, // MRR2 <coproc>,<opc1>,<Rt>,<Rt2>,<CRm>
348 { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // LDRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
349 { "LDRD", 0xe8500000, 0xfe500000, LDRD_REG_IMM8 }, // LDRD <rt>, <rt2>, <label>
355 { "LDREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // LDREXD <Rt>, <Rt2>, [<Rn>]
371 { "STRD", 0xe8400000, 0xfe500000, LDRD_REG_IMM8_SIGNED }, // STRD <rt>, <rt2>, [<rn>, {, #<imm8>]}{!}
377 { "STREXD", 0xe8d00f4f, 0xfff00fff, LDREXD }, // STREXD <Rd>, <Rt>, <Rt2>, [<Rn>]
496 UINT16 Rd, Rn, Rm, Rt, Rt2;
697 Rt2 = (OpCode32 >> 8) & 0xf;
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /external/v8/src/arm64/ |
| assembler-arm64.cc | [all...] |
| constants-arm64.h | 127 V_(Rt2, 14, 10, Bits) /* Load second dest / */ \
[all...] |
| assembler-arm64.h | [all...] |
| simulator-arm64.cc | [all...] |
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| diagnostics.s | 231 @ Out of order Rt/Rt2 operands for ldrexd/strexd
287 @ Out of order Rt/Rt2 operands for ldrd
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
| /toolchain/binutils/binutils-2.25/opcodes/ |
| aarch64-tbl.h | [all...] |
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | [all...] |
| /external/llvm/test/MC/ARM/ |
| diagnostics.s | 300 @ Out of order Rt/Rt2 operands for ldrexd/strexd
374 @ Out of order Rt/Rt2 operands for ldrd
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | [all...] |
| /external/vixl/src/aarch64/ |
| assembler-aarch64.cc | 947 const CPURegister& rt2,
949 LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2));
954 const CPURegister& rt2,
956 LoadStorePair(rt, rt2, dst, StorePairOpFor(rt, rt2));
969 const CPURegister& rt2,
972 // 'rt' and 'rt2' can only be aliased for stores.
973 VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2));
974 VIXL_ASSERT(AreSameSizeAndType(rt, rt2));
[all...] |
| constants-aarch64.h | 59 V_(Rt2, 14, 10, ExtractBits) /* Load/store second register. */ \
[all...] |
| assembler-aarch64.h | [all...] |
| /prebuilts/go/darwin-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
| /prebuilts/go/linux-x86/src/cmd/vendor/golang.org/x/arch/arm/armasm/ |
| tables.go | [all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | [all...] |
