| /external/pcre/dist2/src/ |
| pcre2_jit_misc.c | 222 SLJIT_COMPILE_ASSERT(JIT_NUMBER_OF_COMPILE_MODES == 3, number_of_compile_modes_changed);
|
| pcre2_jit_compile.c | [all...] |
| /external/pcre/dist2/src/sljit/ |
| sljitConfigInternal.h | 716 #ifndef SLJIT_COMPILE_ASSERT
719 #define SLJIT_COMPILE_ASSERT(x, description) \
722 #endif /* !SLJIT_COMPILE_ASSERT */
|
| sljitNativeX86_64.c | 50 SLJIT_COMPILE_ASSERT(reg_map[TMP_REG3] == 9, tmp3_is_9_first);
77 SLJIT_COMPILE_ASSERT(reg_map[TMP_REG3] == 9, tmp3_is_9_second);
192 SLJIT_COMPILE_ASSERT(reg_map[SLJIT_R0] < 8, temporary_reg1_is_loreg);
561 SLJIT_COMPILE_ASSERT(reg_map[SLJIT_R1] == 6 && reg_map[SLJIT_R0] < 8 && reg_map[SLJIT_R2] < 8, args_registers);
575 SLJIT_COMPILE_ASSERT(reg_map[SLJIT_R1] == 2 && reg_map[SLJIT_R0] < 8 && reg_map[SLJIT_R2] < 8, args_registers);
|
| sljitNativeSPARC_32.c | 41 SLJIT_COMPILE_ASSERT(ICC_IS_SET == SET_FLAGS, icc_is_set_and_set_flags_must_be_the_same);
|
| sljitLir.c | 335 SLJIT_COMPILE_ASSERT(
344 SLJIT_COMPILE_ASSERT(SLJIT_I32_OP == SLJIT_F32_OP,
346 SLJIT_COMPILE_ASSERT(SLJIT_REWRITABLE_JUMP != SLJIT_F32_OP,
[all...] |
| sljitNativeX86_32.c | 137 SLJIT_COMPILE_ASSERT(SLJIT_LOCALS_OFFSET >= (2 + 4) * sizeof(sljit_uw), require_at_least_two_words);
|
| sljitNativeX86_common.c | 777 SLJIT_COMPILE_ASSERT(
783 SLJIT_COMPILE_ASSERT(
791 SLJIT_COMPILE_ASSERT((SLJIT_DIVMOD_UW & 0x2) == 0 && SLJIT_DIV_UW - 0x2 == SLJIT_DIVMOD_UW, bad_div_opcode_assignments);
[all...] |
| sljitNativeARM_T2_32.c | [all...] |
| sljitNativeSPARC_common.c | 788 SLJIT_COMPILE_ASSERT((SLJIT_DIVMOD_UW & 0x2) == 0 && SLJIT_DIV_UW - 0x2 == SLJIT_DIVMOD_UW, bad_div_opcode_assignments);
[all...] |
| sljitNativeARM_32.c | [all...] |
| sljitNativeMIPS_common.c | [all...] |
| sljitNativePPC_common.c | 853 SLJIT_COMPILE_ASSERT(A(0) == 0, a0_must_be_0);
[all...] |
| sljitNativeARM_64.c | [all...] |
