| /art/runtime/arch/arm/ |
| registers_arm.h | 56 enum SRegister {
92 std::ostream& operator<<(std::ostream& os, const SRegister& rhs);
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| registers_arm.cc | 37 std::ostream& operator<<(std::ostream& os, const SRegister& rhs) {
41 os << "SRegister[" << static_cast<int>(rhs) << "]";
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| /art/compiler/utils/arm/ |
| assembler_thumb2.h | 199 void vmovsr(SRegister sn, Register rt, Condition cond = AL) OVERRIDE;
200 void vmovrs(Register rt, SRegister sn, Condition cond = AL) OVERRIDE;
201 void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL) OVERRIDE;
202 void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL) OVERRIDE;
205 void vmovs(SRegister sd, SRegister sm, Condition cond = AL) OVERRIDE;
209 bool vmovs(SRegister sd, float s_imm, Condition cond = AL) OVERRIDE;
212 void vldrs(SRegister sd, const Address& ad, Condition cond = AL) OVERRIDE;
213 void vstrs(SRegister sd, const Address& ad, Condition cond = AL) OVERRIDE;
217 void vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) OVERRIDE
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| assembler_arm.h | 584 virtual void vmovsr(SRegister sn, Register rt, Condition cond = AL) = 0;
585 virtual void vmovrs(Register rt, SRegister sn, Condition cond = AL) = 0;
586 virtual void vmovsrr(SRegister sm, Register rt, Register rt2, Condition cond = AL) = 0;
587 virtual void vmovrrs(Register rt, Register rt2, SRegister sm, Condition cond = AL) = 0;
590 virtual void vmovs(SRegister sd, SRegister sm, Condition cond = AL) = 0;
594 virtual bool vmovs(SRegister sd, float s_imm, Condition cond = AL) = 0;
597 virtual void vldrs(SRegister sd, const Address& ad, Condition cond = AL) = 0;
598 virtual void vstrs(SRegister sd, const Address& ad, Condition cond = AL) = 0;
602 virtual void vadds(SRegister sd, SRegister sn, SRegister sm, Condition cond = AL) = 0
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| managed_register_arm.h | 66 // [R..S[ single precision VFP registers (enum SRegister)
77 // [R..S[ single precision VFP registers (enum SRegister)
89 // (enum SRegister), or a VFP double precision register (enum DRegister).
104 constexpr SRegister AsSRegister() const {
106 return static_cast<SRegister>(id_ - kNumberOfCoreRegIds);
109 vixl::aarch32::SRegister AsVIXLSRegister() const {
111 return vixl::aarch32::SRegister(id_ - kNumberOfCoreRegIds);
124 constexpr SRegister AsOverlappingDRegisterLow() const {
127 return static_cast<SRegister>(d_reg * 2);
130 constexpr SRegister AsOverlappingDRegisterHigh() const
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| managed_register_arm.cc | 37 SRegister low = AsOverlappingDRegisterLow();
38 SRegister high = AsOverlappingDRegisterHigh();
39 SRegister other_sreg = other.AsSRegister();
57 low = (r * 2) + kNumberOfCoreRegIds; // Return a SRegister.
84 os << "SRegister: " << static_cast<int>(AsSRegister());
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| constants_arm.h | 387 SRegister SnField() const {
388 return static_cast<SRegister>((Bits(kRnShift, kRnBits) << 1) + Bit(7));
390 SRegister SdField() const {
391 return static_cast<SRegister>((Bits(kRdShift, kRdBits) << 1) + Bit(22));
393 SRegister SmField() const {
394 return static_cast<SRegister>((Bits(kRmShift, kRmBits) << 1) + Bit(5));
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| assembler_thumb2.cc | 427 inline int32_t Thumb2Assembler::VldrsEncoding32(SRegister sd, Register rn, int32_t offset) {
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| assembler_arm_vixl.h | 194 void StoreSToOffset(vixl32::SRegister source, vixl32::Register base, int32_t offset);
202 void LoadSFromOffset(vixl32::SRegister reg, vixl32::Register base, int32_t offset);
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| jni_macro_assembler_arm.cc | 82 static dwarf::Reg DWARFReg(SRegister reg) {
110 __ vpushs(SRegister(CTZ(fp_spill_mask)), POPCOUNT(fp_spill_mask));
112 cfi().RelOffsetForMany(DWARFReg(SRegister(0)), 0, fp_spill_mask, kFramePointerSize);
166 __ vpops(SRegister(CTZ(fp_spill_mask)), POPCOUNT(fp_spill_mask));
168 cfi().RestoreMany(DWARFReg(SRegister(0)), fp_spill_mask);
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| /art/compiler/optimizing/ |
| common_arm.h | 45 inline dwarf::Reg DWARFReg(vixl::aarch32::SRegister reg) {
64 inline vixl::aarch32::SRegister LowSRegisterFrom(Location location) {
66 return vixl::aarch32::SRegister(location.AsFpuRegisterPairLow<vixl::aarch32::SRegister>());
69 inline vixl::aarch32::SRegister HighSRegisterFrom(Location location) {
71 return vixl::aarch32::SRegister(location.AsFpuRegisterPairHigh<vixl::aarch32::SRegister>());
91 inline vixl::aarch32::SRegister SRegisterFrom(Location location) {
93 return vixl::aarch32::SRegister(location.reg());
96 inline vixl::aarch32::SRegister OutputSRegister(HInstruction* instr)
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| code_generator_arm.cc | 54 static constexpr SRegister kFpuCalleeSaves[] =
[all...] |
| code_generator_arm.h | 41 static constexpr SRegister kParameterFpuRegisters[] =
50 static constexpr SRegister kRuntimeParameterFpuRegisters[] = { S0, S1, S2, S3 };
66 class InvokeRuntimeCallingConvention : public CallingConvention<Register, SRegister> {
79 constexpr DRegister FromLowSToD(SRegister reg) {
85 class InvokeDexCallingConvention : public CallingConvention<Register, SRegister> {
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| /art/compiler/utils/arm64/ |
| managed_register_arm64.h | 40 // [D..S[ single precision VFP registers (enum SRegister)
53 // * VFP single precision register (enum SRegister)
74 constexpr SRegister AsSRegister() const {
76 return static_cast<SRegister>(id_ - kNumberOfXRegIds - kNumberOfWRegIds -
91 constexpr SRegister AsOverlappingSRegister() const {
93 return static_cast<SRegister>(AsDRegister());
163 static constexpr Arm64ManagedRegister FromSRegister(SRegister r) {
176 static constexpr Arm64ManagedRegister FromSRegisterD(SRegister r) {
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| jni_macro_assembler_arm64.h | 208 void StoreSToOffset(SRegister source, XRegister base, int32_t offset);
220 void LoadSFromOffset(SRegister dest, XRegister base, int32_t offset);
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| /external/vixl/src/aarch32/ |
| disasm-aarch32.h | 236 virtual DisassemblerStream& operator<<(SRegister reg) {
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| assembler-aarch32.h | 365 SRegister rd,
366 SRegister rm);
368 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm);
385 SRegister rd,
392 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm);
394 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm);
410 SRegister rd,
411 SRegister rm
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| instructions-aarch32.cc | 79 SRegister VRegister::S() const {
81 return SRegister(GetCode());
148 SRegister VRegisterList::GetFirstAvailableSRegister() const {
150 if (((list_ >> i) & 0x1) != 0) return SRegister(i);
152 return SRegister();
157 SRegister first = reglist.GetFirstSRegister();
158 SRegister last = reglist.GetLastSRegister();
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| macro-assembler-aarch32.h | 262 EmitLiteralCondDtSL(DataType dt, SRegister rt) : dt_(dt), rt_(rt) {}
271 SRegister rt_;
834 void Vldr(Condition cond, DataType dt, SRegister rd, RawLiteral* literal) {
841 void Vldr(DataType dt, SRegister rd, RawLiteral* literal) {
844 void Vldr(Condition cond, SRegister rd, RawLiteral* literal) {
847 void Vldr(SRegister rd, RawLiteral* literal) {
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| instructions-aarch32.h | 173 class SRegister;
183 SRegister S() const;
188 class SRegister : public VRegister {
190 SRegister() : VRegister(kNoRegister, 0, kSRegSizeInBits) {}
191 explicit SRegister(uint32_t code)
214 inline std::ostream& operator<<(std::ostream& os, const SRegister reg) {
223 SRegister GetLane(uint32_t lane) const {
227 return SRegister(GetCode() * lane_count + lane);
374 SRegister GetSLane(uint32_t lane) const {
378 return SRegister(GetCode() * lane_count + lane)
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| disasm-aarch32.cc | [all...] |
| /art/runtime/arch/arm64/ |
| registers_arm64.cc | 65 std::ostream& operator<<(std::ostream& os, const SRegister& rhs) {
69 os << "SRegister[" << static_cast<int>(rhs) << "]";
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| registers_arm64.h | 152 enum SRegister {
188 std::ostream& operator<<(std::ostream& os, const SRegister& rhs);
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| /external/vixl/test/aarch32/ |
| test-utils-aarch32.h | 126 // SRegister accessors
174 const SRegister& sreg);
182 bool EqualFP32(float expected, const RegisterDump* core, const SRegister& dreg);
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| test-utils-aarch32.cc | 127 const SRegister& sreg) {
209 const SRegister& sreg) {
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