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    Searched refs:STIR (Results 1 - 4 of 4) sorted by null

  /device/google/contexthub/firmware/os/cpu/cortexm4/inc/cpu/cmsis/
core_cm7.h 392 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
396 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
397 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
438 __O uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */
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core_cm3.h 330 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
334 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
335 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
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core_cm4.h 377 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
381 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
382 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
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core_sc300.h 330 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
334 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
335 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
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