| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 28 for (unsigned su = 0, e = SUnits.size(); su != e; ++su) {
30 if (SUnits[su].getInstr()->isCall())
31 LastSequentialCall = &(SUnits[su]);
33 else if (SUnits[su].getInstr()->isCompare() && LastSequentialCall)
34 SUnits[su].addPred(SDep(LastSequentialCall, SDep::Barrier));
38 /// Check if scheduling of this SU is possible
43 bool VLIWResourceModel::isResourceAvailable(SUnit *SU) {
44 if (!SU || !SU->getInstr()
[all...] |
| HexagonMachineScheduler.h | 86 bool isResourceAvailable(SUnit *SU);
87 bool reserveResources(SUnit *SU);
114 SUnit *SU;
122 SchedCandidate(): SU(nullptr), SCost(0) {}
175 bool checkHazard(SUnit *SU);
177 void releaseNode(SUnit *SU, unsigned ReadyCycle);
181 void bumpNode(SUnit *SU);
185 void removeReady(SUnit *SU);
213 void schedNode(SUnit *SU, bool IsTopNode) override;
215 void releaseTopNode(SUnit *SU) override
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| ResourcePriorityQueue.h | 84 void addNode(const SUnit *SU) override {
88 void updateNode(const SUnit *SU) override {}
104 /// Single cost function reflecting benefit of scheduling SU
106 int SUSchedulingCost (SUnit *SU);
110 void initNumRegDefsLeft(SUnit *SU);
111 void updateNumRegDefsLeft(SUnit *SU);
112 int regPressureDelta(SUnit *SU, bool RawPressure = false);
113 int rawRegPressureDelta (SUnit *SU, unsigned RCId);
121 void remove(SUnit *SU) override;
125 bool isResourceAvailable(SUnit *SU);
[all...] |
| ScheduleDAGInstrs.h | 38 SUnit *SU;
40 VReg2SUnit(unsigned VReg, LaneBitmask LaneMask, SUnit *SU)
41 : VirtReg(VReg), LaneMask(LaneMask), SU(SU) {}
53 unsigned OperandIndex, SUnit *SU)
54 : VReg2SUnit(VReg, LaneMask, SU), OperandIndex(OperandIndex) {}
60 SUnit *SU;
64 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {
[all...] |
| LatencyPriorityQueue.h | 57 void addNode(const SUnit *SU) override {
61 void updateNode(const SUnit *SU) override {
84 void remove(SUnit *SU) override;
93 void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
94 SUnit *getSingleUnscheduledPred(SUnit *SU);
|
| MachineScheduler.h | 212 virtual void schedNode(SUnit *SU, bool IsTopNode) = 0;
216 virtual void releaseTopNode(SUnit *SU) = 0;
219 virtual void releaseBottomNode(SUnit *SU) = 0;
288 /// \brief Add a DAG edge to the given SU with the given predecessor
332 void updateQueues(SUnit *SU, bool IsTopNode);
346 void releaseSucc(SUnit *SU, SDep *SuccEdge);
347 void releaseSuccessors(SUnit *SU);
348 void releasePred(SUnit *SU, SDep *PredEdge);
349 void releasePredecessors(SUnit *SU);
365 // Map each SU to its summary of pressure changes. This array is updated fo
[all...] |
| /external/llvm/lib/CodeGen/ |
| LatencyPriorityQueue.cpp | 55 /// of SU, return it, otherwise return null.
56 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) {
58 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
73 void LatencyPriorityQueue::push(SUnit *SU) {
77 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
79 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
82 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
84 Queue.push_back(SU);
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 70 ResourcePriorityQueue::numberRCValPredInSU(SUnit *SU, unsigned RCId) {
72 for (SUnit::pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
107 unsigned ResourcePriorityQueue::numberRCValSuccInSU(SUnit *SU,
110 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
145 static unsigned numberCtrlDepsInSU(SUnit *SU) {
147 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
155 static unsigned numberCtrlPredInSU(SUnit *SU) {
[all...] |
| ScheduleDAGRRList.cpp | 185 /// IsReachable - Checks if SU is reachable from TargetSU.
186 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
187 return Topo.IsReachable(SU, TargetSU);
190 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
192 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
193 return Topo.WillCreateCycle(SU, TargetSU);
196 /// AddPred - adds a predecessor edge to SUnit SU.
199 void AddPred(SUnit *SU, const SDep &D) {
200 Topo.AddPred(SU, D.getSUnit());
201 SU->addPred(D)
[all...] |
| ScheduleDAGVLIW.cpp | 87 void releaseSucc(SUnit *SU, const SDep &D);
88 void releaseSuccessors(SUnit *SU);
89 void scheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
116 void ScheduleDAGVLIW::releaseSucc(SUnit *SU, const SDep &D) {
131 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
140 void ScheduleDAGVLIW::releaseSuccessors(SUnit *SU) {
142 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
147 releaseSucc(SU, *I);
154 void ScheduleDAGVLIW::scheduleNodeTopDown(SUnit *SU, unsigned CurCycle)
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCHazardRecognizers.h | 31 bool isLoadAfterStore(SUnit *SU);
32 bool isBCTRAfterSet(SUnit *SU);
40 HazardType getHazardType(SUnit *SU, int Stalls) override;
41 bool ShouldPreferAnother(SUnit* SU) override;
42 unsigned PreEmitNoops(SUnit *SU) override;
43 void EmitInstruction(SUnit *SU) override;
79 HazardType getHazardType(SUnit *SU, int Stalls) override;
80 void EmitInstruction(SUnit *SU) override;
|
| PPCHazardRecognizers.cpp | 26 bool PPCDispatchGroupSBHazardRecognizer::isLoadAfterStore(SUnit *SU) {
28 if (isBCTRAfterSet(SU))
31 const MCInstrDesc *MCID = DAG->getInstrDesc(SU);
38 // SU is a load; for any predecessors in this dispatch group, that are stores,
40 for (unsigned i = 0, ie = (unsigned) SU->Preds.size(); i != ie; ++i) {
41 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit());
45 if (!SU->Preds[i].isNormalMemory() && !SU->Preds[i].isBarrier())
49 if (SU->Preds[i].getSUnit() == CurGroup[j])
56 bool PPCDispatchGroupSBHazardRecognizer::isBCTRAfterSet(SUnit *SU) {
[all...] |
| /external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
| SPUHazardRecognizers.h | 33 virtual HazardType getHazardType(SUnit *SU, int Stalls);
34 virtual void EmitInstruction(SUnit *SU);
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGRRList.cpp | 189 /// IsReachable - Checks if SU is reachable from TargetSU.
190 bool IsReachable(const SUnit *SU, const SUnit *TargetSU) {
191 return Topo.IsReachable(SU, TargetSU);
194 /// WillCreateCycle - Returns true if adding an edge from SU to TargetSU will
196 bool WillCreateCycle(SUnit *SU, SUnit *TargetSU) {
197 return Topo.WillCreateCycle(SU, TargetSU);
200 /// AddPred - adds a predecessor edge to SUnit SU.
203 void AddPred(SUnit *SU, const SDep &D) {
204 Topo.AddPred(SU, D.getSUnit());
205 SU->addPred(D)
[all...] |
| ScheduleDAGList.cpp | 81 void ReleaseSucc(SUnit *SU, const SDep &D);
82 void ReleaseSuccessors(SUnit *SU);
83 void ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle);
108 void ScheduleDAGList::ReleaseSucc(SUnit *SU, const SDep &D) {
121 SuccSU->setDepthToAtLeast(SU->getDepth() + D.getLatency());
129 void ScheduleDAGList::ReleaseSuccessors(SUnit *SU) {
131 for (SUnit::succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
136 ReleaseSucc(SU, *I);
143 void ScheduleDAGList::ScheduleNodeTopDown(SUnit *SU, unsigned CurCycle)
[all...] |
| ScheduleDAGFast.cpp | 80 /// AddPred - adds a predecessor edge to SUnit SU.
82 void AddPred(SUnit *SU, const SDep &D) {
83 SU->addPred(D);
86 /// RemovePred - removes a predecessor edge from SUnit SU.
88 void RemovePred(SUnit *SU, const SDep &D) {
89 SU->removePred(D);
93 void ReleasePred(SUnit *SU, SDep *PredEdge);
94 void ReleasePredecessors(SUnit *SU, unsigned CurCycle);
121 DEBUG(for (unsigned su = 0, e = SUnits.size(); su != e; ++su
[all...] |
| ScheduleDAGSDNodes.h | 87 void InitVRegCycleFlag(SUnit *SU);
91 void InitNumRegDefsLeft(SUnit *SU);
95 virtual void ComputeLatency(SUnit *SU);
113 virtual void dumpNode(const SUnit *SU) const;
115 virtual std::string getGraphNodeLabel(const SUnit *SU) const;
129 RegDefIter(const SUnit *SU, const ScheduleDAGSDNodes *SD);
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| ScheduleDAGEmit.cpp | 35 void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
37 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
46 for (SUnit::const_succ_iterator II = SU->Succs.begin(),
47 EE = SU->Succs.end(); II != EE; ++II) {
59 unsigned VRBase = MRI.createVirtualRegister(SU->CopyDstRC);
60 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
|
| LatencyPriorityQueue.cpp | 54 /// of SU, return it, otherwise return null.
55 SUnit *LatencyPriorityQueue::getSingleUnscheduledPred(SUnit *SU) {
57 for (SUnit::const_pred_iterator I = SU->Preds.begin(), E = SU->Preds.end();
72 void LatencyPriorityQueue::push(SUnit *SU) {
76 for (SUnit::const_succ_iterator I = SU->Succs.begin(), E = SU->Succs.end();
78 if (getSingleUnscheduledPred(I->getSUnit()) == SU)
81 NumNodesSolelyBlocking[SU->NodeNum] = NumNodesBlocking;
83 Queue.push_back(SU);
147 SUnit *su = q.pop(); local
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| R600MachineScheduler.cpp | 58 SUnit *SU = nullptr;
98 if (!SU && ((AllowSwitchToAlu && CurInstKind != IDAlu) ||
101 SU = pickAlu();
102 if (!SU && !PhysicalRegCopy.empty()) {
103 SU = PhysicalRegCopy.front();
106 if (SU) {
113 if (!SU) {
115 SU = pickOther(IDFetch);
116 if (SU)
121 if (!SU) {
[all...] |
| SIMachineScheduler.cpp | 178 void SIScheduleBlock::addUnit(SUnit *SU) {
179 NodeNum2Index[SU->NodeNum] = SUnits.size();
180 SUnits.push_back(SU);
187 dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
237 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) {
245 for (SUnit* SU : TopReadySUs) {
250 TryCand.SU = SU;
[all...] |
| GCNHazardRecognizer.h | 50 void EmitInstruction(SUnit *SU) override;
52 HazardType getHazardType(SUnit *SU, int Stalls) override;
54 unsigned PreEmitNoops(SUnit *SU) override;
|
| /external/llvm/lib/Target/ARM/ |
| ARMHazardRecognizer.h | 40 HazardType getHazardType(SUnit *SU, int Stalls) override;
42 void EmitInstruction(SUnit *SU) override;
|
| ARMHazardRecognizer.cpp | 35 ARMHazardRecognizer::getHazardType(SUnit *SU, int Stalls) {
38 MachineInstr *MI = SU->getInstr();
73 return ScoreboardHazardRecognizer::getHazardType(SU, Stalls);
82 void ARMHazardRecognizer::EmitInstruction(SUnit *SU) {
83 MachineInstr *MI = SU->getInstr();
89 ScoreboardHazardRecognizer::EmitInstruction(SU);
|
| /external/swiftshader/third_party/LLVM/include/llvm/CodeGen/ |
| LatencyPriorityQueue.h | 57 void addNode(const SUnit *SU) {
61 void updateNode(const SUnit *SU) {
84 virtual void remove(SUnit *SU);
95 void AdjustPriorityOfUnscheduledPreds(SUnit *SU);
96 SUnit *getSingleUnscheduledPred(SUnit *SU);
|
