| /external/v8/src/arm64/ |
| macro-assembler-arm64-inl.h | 260 void MacroAssembler::Sbcs(const Register& rd,
283 Sbcs(rd, zr, operand);
[all...] |
| macro-assembler-arm64.h | 240 inline void Sbcs(const Register& rd,
[all...] |
| /external/vixl/src/aarch64/ |
| macro-assembler-aarch64.cc | [all...] |
| macro-assembler-aarch64.h | 654 void Sbcs(const Register& rd, const Register& rn, const Operand& operand);
[all...] |
| /external/vixl/test/aarch32/ |
| test-simulator-cond-rd-rn-operand-rm-a32.cc | 135 M(Sbcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-t32.cc | 135 M(Sbcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-const-a32.cc | 135 M(Sbcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-const-t32.cc | 135 M(Sbcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-a32.cc | 135 M(Sbcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to31-t32.cc | 135 M(Sbcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-a32.cc | 135 M(Sbcs) \
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-amount-1to32-t32.cc | 135 M(Sbcs) \
[all...] |
| test-disasm-a32.cc | 542 "sbcs r0, ip\n");
551 "sbcs r0, ip\n");
[all...] |
| test-simulator-cond-rd-rn-operand-rm-shift-rs-a32.cc | 135 M(Sbcs) \
[all...] |
| /external/vixl/src/aarch32/ |
| macro-assembler-aarch32.h | [all...] |
| /art/compiler/optimizing/ |
| intrinsics_arm_vixl.cc | 701 __ Sbcs(temp, out_hi, op2_hi);
[all...] |
| code_generator_arm_vixl.cc | [all...] |
| /external/vixl/test/aarch64/ |
| test-assembler-aarch64.cc | [all...] |
