| /external/llvm/include/llvm/CodeGen/ |
| TargetSchedule.h | 35 MCSchedModel SchedModel;
47 TargetSchedModel(): SchedModel(MCSchedModel::GetDefaultSchedModel()), STI(nullptr), TII(nullptr) {}
70 const MCSchedModel *getMCSchedModel() const { return &SchedModel; }
91 unsigned getProcessorID() const { return SchedModel.getProcessorID(); }
94 unsigned getIssueWidth() const { return SchedModel.IssueWidth; }
102 return SchedModel.getNumProcResourceKinds();
107 return SchedModel.getProcResource(PIdx);
114 return SchedModel.getProcResource(PIdx)->Name;
149 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; }
154 return SchedModel.getProcResource(PIdx)->BufferSize
[all...] |
| ScheduleDAGInstrs.h | 106 TargetSchedModel SchedModel;
243 const TargetSchedModel *getSchedModel() const { return &SchedModel; }
247 if (!SU->SchedClass && SchedModel.hasInstrSchedModel())
248 SU->SchedClass = SchedModel.resolveSchedClass(SU->getInstr());
|
| MachineScheduler.h | 565 void init(ScheduleDAGMI *DAG, const TargetSchedModel *SchedModel);
581 const TargetSchedModel *SchedModel;
651 DAG(nullptr), SchedModel(nullptr), Rem(nullptr), Available(ID, Name+".A"),
700 return RetiredMOps * SchedModel->getMicroOpFactor();
708 return std::max(CurrCycle * SchedModel->getLatencyFactor(),
855 const TargetSchedModel *SchedModel);
860 const TargetSchedModel *SchedModel;
866 Context(C), SchedModel(nullptr), TRI(nullptr) {}
[all...] |
| MachineTraceMetrics.h | 74 TargetSchedModel SchedModel;
112 /// This is an array with SchedModel.getNumProcResourceKinds() entries.
115 /// These numbers have already been scaled by SchedModel.getResourceFactor().
372 // where Kinds = SchedModel.getNumProcResourceKinds().
381 unsigned Factor = SchedModel.getLatencyFactor();
|
| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 24 static cl::opt<bool> EnableSchedModel("schedmodel", cl::Hidden, cl::init(true),
31 return EnableSchedModel && SchedModel.hasInstrSchedModel();
56 SchedModel = sm;
61 unsigned NumRes = SchedModel.getNumProcResourceKinds();
63 ResourceLCM = SchedModel.IssueWidth;
65 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
69 MicroOpFactor = ResourceLCM / SchedModel.IssueWidth;
71 unsigned NumUnits = SchedModel.getProcResource(Idx)->NumUnits;
106 const MCSchedClassDesc *SCDesc = SchedModel.getSchedClassDesc(SchedClass);
117 SCDesc = SchedModel.getSchedClassDesc(SchedClass)
[all...] |
| MachineTraceMetrics.cpp | 60 SchedModel.init(ST.getSchedModel(), &ST, TII);
63 SchedModel.getNumProcResourceKinds());
96 unsigned PRKinds = SchedModel.getNumProcResourceKinds();
107 if (!SchedModel.hasInstrSchedModel())
109 const MCSchedClassDesc *SC = SchedModel.resolveSchedClass(&MI);
114 PI = SchedModel.getWriteProcResBegin(SC),
115 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
126 PRCycles[K] * SchedModel.getResourceFactor(K);
135 unsigned PRKinds = SchedModel.getNumProcResourceKinds();
148 unsigned PRKinds = MTM.SchedModel.getNumProcResourceKinds()
[all...] |
| MachineScheduler.cpp | [all...] |
| MachineCombiner.cpp | 41 MCSchedModel SchedModel;
297 const MCSchedClassDesc *SC = SchedModel.getSchedClassDesc(Idx);
456 SchedModel = STI.getSchedModel();
457 TSchedModel.init(SchedModel, &STI, TII);
|
| ScoreboardHazardRecognizer.cpp | 71 // A nonempty itinerary must have a SchedModel.
72 IssueWidth = ItinData->SchedModel.IssueWidth;
|
| ScheduleDAGInstrs.cpp | 101 SchedModel.init(ST.getSchedModel(), &ST, TII);
314 SchedModel.computeOperandLatency(SU->getInstr(), OperIdx, RegUse,
353 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
462 Dep.setLatency(SchedModel.computeOperandLatency(MI, OperIdx, Use,
506 SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
659 SU->Latency = SchedModel.computeInstrLatency(SU->getInstr());
669 if (SchedModel.hasInstrSchedModel()) {
672 PI = SchedModel.getWriteProcResBegin(SC),
673 PE = SchedModel.getWriteProcResEnd(SC); PI != PE; ++PI) {
674 switch (SchedModel.getProcResource(PI->ProcResourceIdx)->BufferSize)
[all...] |
| TargetInstrInfo.cpp | [all...] |
| EarlyIfConversion.cpp | 592 MCSchedModel SchedModel;
700 unsigned CritLimit = SchedModel.MispredictPenalty/2;
798 SchedModel = STI.getSchedModel();
|
| MachineLICM.cpp | 77 TargetSchedModel SchedModel;
273 SchedModel.init(ST.getSchedModel(), &ST, TII);
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.h | 46 const TargetSchedModel *SchedModel;
57 : SchedModel(SM), TotalPackets(0) {
64 Packet.resize(SchedModel->getIssueWidth());
134 const TargetSchedModel *SchedModel;
155 DAG(nullptr), SchedModel(nullptr), Available(ID, Name+".A"),
168 SchedModel = smodel;
191 const TargetSchedModel *SchedModel;
206 : DAG(nullptr), SchedModel(nullptr), Top(TopQID, "TopQ"),
|
| HexagonMachineScheduler.cpp | 130 if (Packet.size() >= SchedModel->getIssueWidth()) {
204 SchedModel = DAG->getSchedModel();
206 Top.init(DAG, SchedModel);
207 Bot.init(DAG, SchedModel);
281 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
282 if (IssueCount + uops > SchedModel->getIssueWidth())
304 unsigned Width = SchedModel->getIssueWidth();
347 IssueCount += SchedModel->getNumMicroOps(SU->getInstr());
|
| /external/llvm/include/llvm/MC/ |
| MCInstrItineraries.h | 111 MCSchedModel SchedModel; ///< Basic machine properties.
118 InstrItineraryData() : SchedModel(MCSchedModel::GetDefaultSchedModel()),
124 : SchedModel(SM), Stages(S), OperandCycles(OS), Forwardings(F),
125 Itineraries(SchedModel.InstrItineraries) {}
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64StorePairSuppress.cpp | 33 TargetSchedModel SchedModel;
83 SchedModel.getMCSchedModel()->getSchedClassDesc(SCIdx);
125 SchedModel.init(ST.getSchedModel(), &ST, TII);
131 if (!SchedModel.hasInstrSchedModel()) {
|
| AArch64ConditionalCompares.cpp | 723 MCSchedModel SchedModel;
843 unsigned DelayLimit = SchedModel.MispredictPenalty * 3 / 4;
894 SchedModel = MF.getSubtarget().getSchedModel();
|
| /external/llvm/lib/MC/ |
| MCSubtargetInfo.cpp | 96 assert(Found->Value && "Missing processor SchedModel value");
102 const MCSchedModel SchedModel = getSchedModelForCPU(CPU);
103 return InstrItineraryData(SchedModel, Stages, OperandCycles, ForwardingPaths);
|
| /external/llvm/include/llvm/Target/ |
| TargetSubtargetInfo.h | 119 const TargetSchedModel *SchedModel) const {
|
| TargetInstrInfo.h | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMSubtarget.cpp | 147 SchedModel = getSchedModelForCPU(CPUString);
279 return SchedModel.MispredictPenalty;
294 // This overrides the PostRAScheduler bit in the SchedModel for any CPU.
|
| ARMBaseInstrInfo.h | 344 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
349 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
|
| ARMSubtarget.h | 331 /// SchedModel - Processor specific instruction costs.
332 MCSchedModel SchedModel;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 129 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
|
