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    Searched refs:SchedReads (Results 1 - 2 of 2) sorted by null

  /external/llvm/utils/TableGen/
CodeGenSchedule.h 111 /// 2) An implied class with a list of SchedWrites and SchedReads that are
116 /// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
242 std::vector<CodeGenSchedRW> SchedReads;
325 assert(Idx < SchedReads.size() && "bad SchedRead index");
326 assert(SchedReads[Idx].isValid() && "invalid SchedRead");
327 return SchedReads[Idx];
CodeGenSchedule.cpp 100 // defined, and populate SchedReads and SchedWrites vectors. Implicit
207 SchedReads.resize(1);
286 SchedReads.emplace_back(SchedReads.size(), *SRI);
312 for (unsigned RIdx = 0, REnd = SchedReads.size(); RIdx != REnd; ++RIdx) {
314 SchedReads[RIdx].dump();
342 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites;
353 for (unsigned i = 0, e = SchedReads.size(); i < e; ++i) {
354 Record *ReadDef = SchedReads[i].TheDef;
462 std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites
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